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AM41DL32X8G 데이터시트(PDF) 27 Page - Advanced Micro Devices |
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AM41DL32X8G 데이터시트(HTML) 27 Page - Advanced Micro Devices |
27 / 66 page 26 Am41DL32x8G September 5, 2002 PR ELI M I NARY Table 13. System Interface String Table 14. Device Geometry Definition Addresses (Word Mode) Addresses (Byte Mode) Data Description 1Bh 36h 0027h V CC Min. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Ch 38h 0036h V CC Max. (write/erase) D7–D4: volt, D3–D0: 100 millivolt 1Dh 3Ah 0000h V PP Min. voltage (00h = no VPP pin present) 1Eh 3Ch 0000h VPP Max. voltage (00h = no VPP pin present) 1Fh 3Eh 0004h Typical timeout per single byte/word write 2N µs 20h 40h 0000h Typical timeout for Min. size buffer write 2 N µs (00h = not supported) 21h 42h 000Ah Typical timeout per individual block erase 2N ms 22h 44h 0000h Typical timeout for full chip erase 2 N ms (00h = not supported) 23h 46h 0005h Max. timeout for byte/word write 2N times typical 24h 48h 0000h Max. timeout for buffer write 2 N times typical 25h 4Ah 0004h Max. timeout per individual block erase 2N times typical 26h 4Ch 0000h Max. timeout for full chip erase 2 N times typical (00h = not supported) Addresses (Word Mode) Addresses (Byte Mode) Data Description 27h 4Eh 0016h Device Size = 2 N byte 28h 29h 50h 52h 0002h 0000h Flash Device Interface description (refer to CFI publication 100) 2Ah 2Bh 54h 56h 0000h 0000h Max. number of byte in multi-byte write = 2 N (00h = not supported) 2Ch 58h 0002h Number of Erase Block Regions within device 2Dh 2Eh 2Fh 30h 5Ah 5Ch 5Eh 60h 0007h 0000h 0020h 0000h Erase Block Region 1 Information (refer to the CFI specification or CFI publication 100) 31h 32h 33h 34h 62h 64h 66h 68h 003Eh 0000h 0000h 0001h Erase Block Region 2 Information 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information |
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