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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM29BDS643G 데이터시트(HTML) 22 Page - Advanced Micro Devices |
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AM29BDS643G 데이터시트(HTML) 22 Page - Advanced Micro Devices |
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20 Am29BDS643G 25692A2 May 8, 2006 D A TA SH EE T COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 10 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the rising edge of AVD#. All data is latched on the rising edge of WE#. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data in asynchronous mode. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector. After com- pleting a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. Se e a l so Re qu ir em en t s f o r Asyn chr o n o u s Read Operation (Non-Burst) and Requirements for Synchronous (Burst) Read Operation in the Device Bus Operations section for more information. The Asynchronous Read and Synchronous/Burst Read tables provide the read parameters, and Figures 9 and 11 show the timings. Set Configuration Register Command Se- quence The configuration register command sequence instructs the device to set a particular number of clock cycles for the initial access in burst mode. The number of wait states that should be programmed into the device is directly related to the clock frequency. The first two cycles of the command sequence are for unlock purposes. On the third cycle, the system should write C0h to the address associated with the intended wait state setting (see Table 8). Address bits A16–A12 determine the setting. Note that addresses A19–A17 are shown as “0” but are actually don’t care. Table 8. Burst Modes Note: The burst mode is set in the third cycle of the Set Wait State command sequence. Upon power up, the device defaults to the maximum seven cycle wait state setting. It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting. Handshaking Feature The host system should set address bits A16–A12 to “00010” for a clock frequency of 40 MHz or to “00011” for a clock frequency of 54 or 66 MHz, assuming con- tinuous burst is desired in both cases. Table 9 describes the typical number of clock cycles (wait states) for various conditions. Burst Mode Third Cycle Addresses for Wait States Wait States 01 234 5 Clock Cycles 23 456 7 Continuous 00555h 01555h 02555h 03555h 04555h 05555h 8-word Linear 08555h 09555h 0A555h 0B555h 0C555h 0D555h 16-word Linear 10555h 11555h 12555h 13555h 14555h 15555h 32-word Linear 18555h 19555h 1A555h 1B555h 1C555h 1D555h |
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