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AM29BDS643G 데이터시트(HTML) 27 Page - Advanced Micro Devices

부품명 AM29BDS643G
상세내용  64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM29BDS643G 데이터시트(HTML) 27 Page - Advanced Micro Devices

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May 8, 2006 25692A2
Am29BDS643G
25
D A TA
SH EE T
Table 10.
Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A21–A12 uniquely select any sector.
BA = Address of the bank (A21, A20) that is being switched to
autoselect mode, is in bypass mode, or is being erased.
SLA = Address of the sector to be locked. Set sector address (SA) and
either A6 = 1 for unlocked or A6 = 0 for locked.
CR = Configuration Register set by address bits A16–A12.
Notes:
1.
See Table 1 for description of bus operations.
2.
All values are in hexadecimal.
3.
Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
4.
Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
5.
Unless otherwise noted, address bits A21–A12 are don’t cares.
6.
No unlock or command cycles required when bank is reading
array data.
7.
The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
8.
The fourth cycle of the autoselect command sequence is a read
cycle. The system must read device IDs across the 4th, 5th, and
6th cycles, The system must provide the bank address. See the
Autoselect Command Sequence section for more information.
9.
The data is 0000h for an unlocked sector and 0001h for a locked
sector
10. The data is 0043h for handshaking enabled.
11. The Unlock Bypass command sequence is required prior to this
command sequence.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. The Erase Resume command is valid only during the Erase
Suspend mode, and requires the bank address.
15. The addresses in the third cycle must contain, on A12–A16, the
additional wait counts to be set. See “Set Configuration Register
Command Sequence”.
16. Command is valid when device is ready to read array data or
when device is in autoselect moe.
Command Sequence
(Note 1)
Bus Cycles (Notes 2–5)
First
Second
Third
Fourth
Fifth
Sixth
Addr Data Addr Data
Addr
Data
Addr
Data
Addr Data Addr Data
Asynchronous Read (Note 6)
1
RA
RD
Reset (Note 7)
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
(BA)555
90
(BA)X00
0001
Device ID
6
555
AA
2AA
55
(BA)555
90
(BA)X01
227E
(BA)
X0E
2202
(BA)
X0F
2200
Sector Lock Verify (Note 9)
4
555
AA
2AA
55
(SA)555
90
(SA)X02 0000 0001
Handshaking Option (Note 10)
4
555
AA
2AA
55
(BA)555
90
(BA)X03 0042 0043
Program
4
555
AA
2AA
55
555
A0
PA
Data
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass Program (Note 11)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 12)
2
BA
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
Sector Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
SA
30
Erase Suspend (Note 13)
1
BA
B0
Erase Resume (Note 14)
1
BA
30
Sector Lock/Unlock
3
XXX
60
XXX
60
SLA
60
Set Configuration Register (Note 15)
3
555
AA
2AA
55
(CR)555
C0
Enable PS Mode
3
555
AA
2AA
55
555
70
CFI Query (Note 16)
1
55
98


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