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AM29BDS643G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 3 Page - Advanced Micro Devices

๋ถ€ํ’ˆ๋ช… AM29BDS643G
์ƒ์„ธ๋‚ด์šฉ  64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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DATA SHEET
Publication# 25692 Revision: A Amendment: 2
Issue Date: May 8, 2006
Am29BDS643G
64 Megabit (4 M x 16-Bit)
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
DISTINCTIVE CHARACTERISTICS
โ–  Single 1.8 volt read, program and erase (1.7 to
1.9 volt)
โ–  Multiplexed Data and Address for reduced I/O
count
โ€” A0โ€“A15 multiplexed as D0โ€“D15
โ€” Addresses are latched by AVD# control input
when CE# low
โ–  Simultaneous Read/Write operation
โ€” Data can be continuously read from one bank
while executing erase/program functions in other
bank
โ€” Zero latency between read and write operations
โ–  Read access times at 66/54/40 MHz
โ€” Burst access times of 11/13.5/20 ns @ 30 pF
at industrial temperature range
โ€” Asynchronous random access times
of 55/70/70 ns @ 30 pF
โ€” Synchronous random access times
of 71/87.5/95 ns @ 30 pF
โ–  Burst length
โ€” Continuous linear burst
โ€” 8/16/32 word linear burst with wrap around
โ–  Power dissipation (typical values, 8 bits
switching, CL = 30 pF)
โ€” Burst Mode Read: 25 mA
โ€” Simultaneous Operation: 40 mA
โ€” Program/Erase: 15 mA
โ€” Standby mode: 0.2 ยตA
โ–  Sector Architecture
โ€” Eight 8 Kword sectors and one hundred
twenty-six 32 Kword sectors
โ€” Banks A and B each contain four 8 Kword
sectors and thirty-one 32 Kword sectors; Banks
C and D each contain thirty-two 32 Kword
sectors
โ–  Sector Protection
โ€” Software command sector locking
โ€” WP# protects the last two boot sectors
โ€” All sectors locked when VPP = VIL
โ–  Handshaking feature
โ€” Provides host system with minimum possible
latency by monitoring RDY
โ–  Supports Common Flash Memory
Interface (CFI)
โ–  Software command set compatible with JEDEC
42.4 standards
โ€” Backwards compatible with Am29F and Am29LV
families
โ–  Manufactured on 0.17 ยตm process technology
โ–  Minimum 1 million erase cycle guarantee
per sector
โ–  20-year data retention at 125ยฐC
โ€” Reliable operation for the life of the system
โ–  Embedded Algorithms
โ€” Embedded Erase algorithm automatically
preprograms and erases the entire chip or any
combination of designated sectors
โ€” Embedded Program algorithm automatically
writes and verifies data at specified addresses
โ–  Data# Polling and toggle bits
โ€” Provides a software method of detecting
program and erase operation completion
โ–  Erase Suspend/Resume
โ€” Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
โ–  Hardware reset input (RESET#)
โ€” Hardware method to reset the device for reading
array data
โ–  CMOS compatible inputs and outputs
โ–  Package
โ€” 44-ball Very Thin FBGA
This product has been retired and is not recommended for designs. For new designs, S29NS064J supersedes Am29BDS643G. Please refer to the S29NS-J family data sheet for specifi-
cations and ordering information. Availability of this document is retained for reference and historical purposes only.


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