์ „์ž๋ถ€ํ’ˆ ๋ฐ์ดํ„ฐ์‹œํŠธ ๊ฒ€์ƒ‰์—”์ง„
  Korean  โ–ผ

Delete All
ON OFF
ALLDATASHEET.CO.KR

X  

Preview PDF Download HTML

AM29BDS643G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 5 Page - Advanced Micro Devices

๋ถ€ํ’ˆ๋ช… AM29BDS643G
์ƒ์„ธ๋‚ด์šฉ  64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
Download  49 Pages
Scroll/Zoom Zoom In 100% Zoom Out
์ œ์กฐ์‚ฌ  AMD [Advanced Micro Devices]
ํ™ˆํŽ˜์ด์ง€  http://www.amd.com
Logo 

AM29BDS643G ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 5 Page - Advanced Micro Devices

 
Zoom Inzoom in Zoom Outzoom out
/ 49 page
 5 / 49 page
background image
May 8, 2006 25692A2
Am29BDS643G
3
D A TA
SH EE T
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram of
Simultaneous Operation Circuit . . . . . . . . . . . . . . 5
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 6
Special Handling Instructions for FBGA Package .................... 6
Input/Output Descriptions . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations .......................................................9
Requirements for Asynchronous Read Operation (Non-Burst) 9
Requirements for Synchronous (Burst) Read Operation .......... 9
Continuous Burst ...................................................................... 9
8-, 16-, and 32-Word Linear Burst with Wrap Around ............ 10
Table 2. Burst Address Groups .......................................................10
Programmable Wait State ...................................................... 10
Handshaking Feature ............................................................. 10
Power Saving Function ........................................................... 11
Simultaneous Read/Write Operations with Zero Latency ....... 11
Writing Commands/Command Sequences ............................ 11
Accelerated Program Operation ............................................. 11
Autoselect Functions .............................................................. 11
Automatic Sleep Mode ........................................................... 12
RESET#: Hardware Reset Input ............................................. 12
Output Disable Mode .............................................................. 12
Hardware Data Protection ...................................................... 12
Low VCC Write Inhibit ............................................................ 12
Write Pulse โ€œGlitchโ€ Protection ............................................... 12
Logical Inhibit .......................................................................... 12
Common Flash Memory Interface (CFI) . . . . . . . 13
Table 3. CFI Query Identification String ..........................................13
Table 4. System Interface String .....................................................14
Table 5. Device Geometry Definition ..............................................14
Table 6. Primary Vendor-Specific Extended Query ........................15
Table 7. Sector Address Table ........................................................16
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20
Reading Array Data ................................................................ 20
Set Configuration Register Command Sequence ................... 20
Table 8. Burst Modes ......................................................................20
Handshaking Feature ............................................................. 20
Table 9. Wait States for Handshaking .............................................21
Enable PS (Power Saving) Mode Command Sequence ........ 21
Sector Lock/Unlock Command Sequence .............................. 21
Reset Command ..................................................................... 21
Autoselect Command Sequence ............................................ 21
Program Command Sequence ............................................... 22
Unlock Bypass Command Sequence ..................................... 22
Figure 1. Program Operation .......................................................... 23
Chip Erase Command Sequence ........................................... 23
Sector Erase Command Sequence ........................................ 23
Erase Suspend/Erase Resume Commands ........................... 24
Figure 2. Erase Operation.............................................................. 24
Table 10. Command Definitions .................................................... 25
Write Operation Status . . . . . . . . . . . . . . . . . . . . 26
DQ7: Data# Polling ................................................................. 26
Figure 3. Data# Polling Algorithm .................................................. 26
DQ6: Toggle Bit I .................................................................... 27
Figure 4. Toggle Bit Algorithm........................................................ 27
DQ2: Toggle Bit II ................................................................... 28
Table 11. DQ6 and DQ2 Indications .............................................. 28
Reading Toggle Bits DQ6/DQ2 ............................................... 28
DQ5: Exceeded Timing Limits ................................................ 28
DQ3: Sector Erase Timer ....................................................... 29
Table 12. Write Operation Status ................................................... 29
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 30
Figure 5. Maximum Negative Overshoot Waveform ...................... 30
Figure 6. Maximum Positive Overshoot Waveform........................ 30
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 30
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 7. Test Setup....................................................................... 32
Table 13. Test Specifications ......................................................... 32
Key to Switching Waveforms. . . . . . . . . . . . . . . . 32
Switching Waveforms. . . . . . . . . . . . . . . . . . . . . . 32
Figure 8. Input Waveforms and
Measurement Levels...................................................................... 32
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33
Synchronous/Burst Read ........................................................ 33
Figure 9. Burst Mode Read (66 and 54 MHz) ................................ 33
Figure 10. Burst Mode Read (40 MHz) .......................................... 34
Asynchronous Read ............................................................... 35
Figure 11. Asynchronous Mode Read............................................ 35
Figure 12. Reset Timings ............................................................... 36
Erase/Program Operations ..................................................... 37
Figure 13. Program Operation Timings.......................................... 38
Figure 14. Chip/Sector Erase Operations ...................................... 39
Figure 15. Accelerated Unlock Bypass Programming Timing........ 40
Figure 16. Data# Polling Timings (During Embedded Algorithm) .. 41
Figure 17. Toggle Bit Timings (During Embedded Algorithm)........ 41
Figure 18. 8-, 16-, and 32-Word Linear Burst
Address Wrap Around.................................................................... 42
Figure 19. Latency with Boundary Crossing (54 MHz and 66 MHz) 42
Figure 20. Initial Access with Power Saving (PS)
Function and Address Boundary Latency ...................................... 43
Figure 21. Example of Extended Valid Address Reducing Wait State
Usage............................................................................................. 43
Figure 22. Back-to-Back Read/Write Cycle Timings ...................... 44
Erase and Programming Performance . . . . . . . 45
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Physical Dimensions* . . . . . . . . . . . . . . . . . . . . . 46
VDA044โ€”44-Ball Very Thin Fine-Pitch Ball Grid Array
(FBGA) 9.2 x 8.0 mm Package ............................................... 46
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 47


Html Pages

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49 


๋ฐ์ดํ„ฐ์‹œํŠธ Download



๊ด€๋ จ ๋ถ€ํ’ˆ๋ช…

๋ถ€ํ’ˆ๋ช…์ƒ์„ธ๋‚ด์šฉHtml View์ œ์กฐ์‚ฌ
AM29BDS128H128 or 64 Megabit 8 M or 4 M x 16-Bit CMOS 1.8 Volt-only Simultaneous Read/Write Burst Mode Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29BDS320G32 Megabit 2 M x 16-Bit 1.8 Volt-only Simultaneous Read/Write Burst Mode Flash Memory 1 2 3 4 5 MoreSPANSION
AM42BDS6408HCMOS 1.8 Volt-only Simultaneous Read/Write Burst Mode Flash Memory and 8 Mbit 512 K x 16-Bit SRAM 1 2 3 4 5 MoreSPANSION
AM29BDS640G64 Megabit 4 M x 16-Bit 1.8 Volt-only Simultaneous Read/Write Burst Mode Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM42BDS640AG64 Megabit 4 M x 16-Bit CMOS 1.8 Volt-only Simultaneous Operation Burst Mode Flash Memory and 16 Mbit 1 M x 16-Bit Static RAM 1 2 3 4 5 MoreAdvanced Micro Devices
AM29PDL129H128 Megabit 8 M x 16-Bit CMOS 3.0 Volt-only Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIO 1 2 3 4 5 MoreAdvanced Micro Devices
AM29PDL127H128 Megabit 8 M x 16-Bit CMOS 3.0 Volt-only Page Mode Simultaneous Read/Write Flash Memory with Enhanced VersatileIOTM Control 1 2 3 4 5 MoreAdvanced Micro Devices
AM29PDS322D32 Megabit 2 M x 16-Bit CMOS 1.8 Volt-only 1.8 V to 2.2 V Simultaneous Read/Write Page-Mode Boot Sector Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM29BDD160G_0616 Megabit 1 M x 16-bit/512 K x 32-Bit CMOS 2.5 Volt-only Burst Mode Dual Boot Simultaneous Read/Write Flash Memory 1 2 3 4 5 MoreAdvanced Micro Devices
AM41PDS3224D32 Megabit 2 M x 16-Bit CMOS 1.8 Volt-only Simultaneous Operation Page Mode Flash Memory and 4 Mbit 512 K x 8-Bit/256 K x 16-Bit Static RAM 1 2 3 4 5 MoreAdvanced Micro Devices

๋งํฌ URL



Privacy Policy
ALLDATASHEET.CO.KR
ALLDATASHEET ๊ฐ€ ๊ท€ํ•˜์— ๋„์›€์ด ๋˜์…จ๋‚˜์š”?  [ DONATE ]  

Alldatasheet๋Š”?   |   ๊ด‘๊ณ ๋ฌธ์˜    |   ์šด์˜์ž์—๊ฒŒ ์—ฐ๋ฝํ•˜๊ธฐ   |   ๊ฐœ์ธ์ •๋ณด์ทจ๊ธ‰๋ฐฉ์นจ   |   ์ฆ๊ฒจ์ฐพ๊ธฐ   |   ๋งํฌ๊ตํ™˜   |   ์ œ์กฐ์‚ฌ๋ณ„ ๊ฒ€์ƒ‰
All Rights Reservedยฉ Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn