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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM42DL640AG85IT 데이터시트(PDF) 56 Page - Advanced Micro Devices |
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AM42DL640AG85IT 데이터시트(HTML) 56 Page - Advanced Micro Devices |
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56 / 62 page  October 22, 2002 Am42DL640AG 55 PR E L I M I N A R Y AC CHARACTERISTICS SRAM Write Cycle Notes: 1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing. 2. t CW is measured from CE1#s going low to the end of write. 3. t WR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high. 4. t AS is measured from the address valid to the beginning of write. 5. A write occurs during the overlap (t WP) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A write ends at the earliest transition when CE1#s goes high and WE# goes high. The t WP is measured from the beginning of write to the end of write. Figure 31. SRAM Write Cycle—WE# Control Parameter Symbol Description Speed Unit 71 70 85 t WC Write Cycle Time Min 55 70 85 ns t Cw Chip Enable to End of Write Min 45 60 70 ns t AS Address Setup Time Min 0 ns t AW Address Valid to End of Write Min 45 60 70 ns t BW UB#s, LB#s to End of Write Min 45 60 70 ns tWP Write Pulse Time Min 40 50 60 ns t WR Write Recovery Time Min 0 ns t WHZ Write to Output High-Z Min 0 ns Max 202025 ns t DW Data to Write Time Overlap Min 25 30 35 ns t DH Data Hold from Write Time Min 0 ns t OW End Write to Output Low-Z min 5 ns Address CE1#s Data Undefined WE# Data In Data Out tWC tCW (See Note 1) tAW High-Z High-Z Data Valid CE2s tCW (See Note 1) tWP (See Note 4) tAS (See Note 3) tWR tDW tDH tOW tWHZ |
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