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AM29BDS640G 데이터시트(HTML) 4 Page - Advanced Micro Devices

부품명 AM29BDS640G
상세내용  64 Megabit (4 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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제조사  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
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AM29BDS640G 데이터시트(HTML) 4 Page - Advanced Micro Devices

 
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2Am29BDS640G
25903C2 May 9, 2006
Data
Sheet
General Description
The Am29BDS640G is a 64 Mbit, 1.8 Volt-only, simultaneous Read/Write, Burst Mode
Flash memory device, organized as 4,194,304 words of 16 bits each. This device uses a
single VCC of 1.65 to 1.95 V to read, program, and erase the memory array. The device
supports Enhanced VIO to offer up to 3V compatible inputs and outputs. A 12.0-volt VID
may be used for faster program performance if desired. The device can also be pro-
grammed in standard EPROM programmers.
At 54 MHz, the device provides a burst access of 13.5 ns at 30 pF with a latency of 87.5
ns at 30 pF. At 40 MHz, the device provides a burst access of 20 ns at 30 pF with a la-
tency of 95 ns at 30 pF. The device operates within the industrial temperature range of -
40°C to +85°C. The device is offered in the 80-ball FBGA package.
The Simultaneous Read/Write architecture provides simultaneous operation by divid-
ing the memory space into four banks. The device can improve overall system perfor-
mance by allowing a host system to program or erase in one bank, then immediately and
simultaneously read from another bank, with zero latency. This releases the system from
waiting for the completion of program or erase operations.
The device is divided as shown in the following table:
The Enhanced VersatileIO™ (VIO) control allows the host system to set the voltage levels
that the device generates at its data outputs and the voltages tolerated at its data inputs
to the same voltage level that is asserted on the VIO pin. This allows the device to operate
in 1.8 V and 3 V system environments as required.
The device uses Chip Enable (CE#), Write Enable (WE#), Address Valid (AVD#) and Out-
put Enable (OE#) to control asynchronous read and write operations. For burst opera-
tions, the device additionally requires Ready (RDY), and Clock (CLK). This
implementation allows easy interface with minimal glue logic to a wide range of micropro-
cessors/microcontrollers for high performance read operations.
The burst read mode feature gives system designers flexibility in the interface to the de-
vice. The user can preset the burst length and wrap through the same memory space, or
read the flash array in continuous mode.
The clock polarity feature provides system designers a choice of active clock edges, either
rising or falling. The active clock edge initiates burst accesses and determines when data
will be output.
The device is entirely command set compatible with the JEDEC 42.4 single-power-
supply Flash standard. Commands are written to the command register using standard
microprocessor write timing. Register contents serve as inputs to an internal state-ma-
chine that controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out
of the device is similar to reading from other Flash or EPROM devices.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for
any period of time to read data from, or program data to, any sector that is not selected
for erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal
state machine to reading array data. The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the device, enabling the system microproces-
sor to read boot-up firmware from the Flash memory device.
The host system can detect whether a program or erase operation is complete by using
the device status bit DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or
erase cycle has been completed, the device automatically returns to reading array data.
Bank
Quantity
Size
A
48 Kwords
31
32 Kwords
B
32
32 Kwords
C
32
32 Kwords
D
31
32 Kwords
48 Kwords


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