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AM29BDS640GBC8WSI 데이터시트(PDF) 75 Page - Advanced Micro Devices

부품명 AM29BDS640GBC8WSI
상세설명  64 Megabit (4 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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제조업체  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

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May 9, 2006 25903C2
Am29BDS640G
73
Data
Sheet
Revision Summary
Revision A (February 13, 2002)
Initial release.
Revision A+1 (February 19, 2002)
Automatic Sleep Mode
Clarified description to indicate that sleep mode is activated when the first CLK
edge occurs after tACC.
Figure 20, Asynchronous Program Operation Timings
Modified to show that CLK is don’t care prior to AVD# going low, and that AVD#
must not be low before CE# transitions low.
Revision A+2 (February 27, 2002)
Figure 21, Asynchronous Program Operation Timings
Extended don’t care section of CLK to falling edge of WE#.
Revision A+3 (May 9, 2002)
Requirements for Synchronous (Burst) Read Operation
Shifted address, clock, and data cycle references in third paragraph up by one.
Table 4, System Interface String
Corrected data for address 23h.
Table 9, Initial Access Cycles vs. Frequency
Added table.
Autoselect Command Sequence
Added bottom boot device IDs to table.
Table 13, Command Definitions
Added bottom boot device IDs to table.
RDY: Ready
Corrected address boundary from 63rd word/3Eh to 64th word/3Fh.
DC Characteristics
Added VIO = VIO min to test conditions for VOL and VOH in table.
Erase/Program Operations table
Added specifications for parameters tCSW1, tCSW2, tCHW, tAHC.
Figures 21, 23
Added note to indicate AVD# must toggle during command sequence unlock cy-
cles. Added tCSW1 to 21.
Figures 22, 24
Added figures, which show different timings between addresses, CLK, WE#, and
AVD#.
Figures 25, 27, 28
Added note to indicate AVD# must toggle during data reads.
Figures 30, 31
Shifted address, clock, and data cycle counts up by one.


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