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AM29BDS640GTC9WSI 데이터시트(PDF) 60 Page - Advanced Micro Devices |
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AM29BDS640GTC9WSI 데이터시트(HTML) 60 Page - Advanced Micro Devices |
60 / 77 page 58 Am29BDS640G 25903C2 May 9, 2006 Data Sheet AC Characteristics Erase/Program Operations Notes: 1. Not 100% tested. 2. In asynchronous timing, addresses are latched on the falling edge of WE#. In synchronous mode, addresses are latched on the first of either the rising edge of AVD# or the active edge of CLK. 3. See the “Erase and Programming Performance” section for more information. 4. Does not include the preprogramming time. Parameter Description All Speed Options Unit JEDEC Standard tAVAV tWC Write Cycle Time (Note 1) Min 80 ns tAVWL tAS Address Setup Time (Note 2) Synchronous Min 5 ns Asynchronous 0 tWLAX tAH Address Hold Time (Note 2) Synchronous Min 7 ns Asynchronous 45 tACS Address Setup Time to CLK (Note 2) Min 5 ns tACH Address Hold Time to CLK (Note 2) Min 7 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write Min 0 ns tCAS CE# Setup Time to AVD# Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 50 ns tWHWL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 3) Typ 8 µs tWHWH1 tWHWH1 Accelerated Programming Operation (Note 3) Typ 2.5 µs tWHWH2 tWHWH2 Sector Erase Operation (Notes 3, 4) Typ 0.2 sec Chip Erase Operation (Notes 3, 4) 26.8 tVID VACC Rise and Fall Time Min 500 ns tVIDS VACC Setup Time (During Accelerated Programming) Min 1 µs tVCS VCC Setup Time Min 50 µs tCSW1 Clock Setup Time to WE# (Asynchronous) Min 5 ns tCSW2 Clock Setup Time to WE# (Synchronous) Min 1 ns tCHW Clock Hold Time from WE# Max 1 ns tELWL tCS CE# Setup Time to WE# Min 0 ns tAVSW AVD# Setup Time to WE# Min 5 ns tAVHW AVD# Hold Time to WE# Min 5 ns tAVHC AVD# Hold Time to CLK Min 5 ns tAVDP AVD# Low Time Min 12 ns |
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