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AM41PDS3224D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - Advanced Micro Devices

๋ถ€ํ’ˆ๋ช… AM41PDS3224D
์ƒ์„ธ๋‚ด์šฉ  32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
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์ œ์กฐ์‚ฌ  AMD [Advanced Micro Devices]
ํ™ˆํŽ˜์ด์ง€  http://www.amd.com
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AM41PDS3224D ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - Advanced Micro Devices

 
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PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 26085
Rev: A Amendment/+1
Issue Date: May 13, 2002
Refer to AMDโ€™s Website (www.amd.com) for the latest information.
Am41PDS3224D
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29PDS322D 32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Page Mode Flash Memory and 4 Mbit (512 K x 8-Bit/256 K x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
โ–  Power supply voltage of 1.8 to 2.2 volt
โ–  High performance
โ€” Access time as fast as 100 ns flash, 70 ns SRAM
โ–  Package
โ€” 73-Ball FBGA
โ–  Operating Temperature
โ€” โ€“40ยฐC to +85ยฐC
Flash Memory Features
ARCHITECTURAL ADVANTAGES
โ–  Simultaneous Read/Write operations
โ€” Data can be continuously read from one bank while
executing erase/program functions in other bank.
โ€” Zero latency between read and write operations
โ–  Page Mode Operation
โ€” 4 word page allows fast asynchronous reads
โ–  Dual Bank architecture
โ€” One 4 Mbit bank and one 28 Mbit bank
โ–  SecSi (Secured Silicon) Sector: Extra 64 KByte sector
โ€” Factory locked and identifiable: 16 byte Electronic Serial
Number available for factory secure, random ID; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
โ€” Customer lockable: Can be read, programmed, or erased
just like other sectors. Once locked, data cannot be changed
โ–  Zero Power Operation
โ€” Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
โ–  Top or bottom boot block
โ–  Manufactured on 0.23 ยตm process technology
โ–  Compatible with JEDEC standards
โ€” Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
โ–  High performance
โ€” Random access time of 100 ns at 1.8 V to 2.2 V V
CC
โ–  Ultra low power consumption (typical values)
โ€” 2.5 mA active read current at 1 MHz for initial page read
โ€” 24 mA active read current at 10 MHz for initial page read
โ€” 0.5 mA active read current at 10 MHz for intra-page read
โ€” 1 mA active read current at 20 MHz for intra-page read
โ€” 200 nA in standby or automatic sleep mode
โ– 
Minimum 1 million write cycles guaranteed per sector
โ– 
20 year data retention at 125
ยฐC
โ€” Reliable operation for the life of the system
SOFTWARE FEATURES
โ– 
Data Management Software (DMS)
โ€” AMD-supplied software manages data programming,
enabling EEPROM emulation
โ€” Eases historical sector erase flash limitations
โ– 
Erase Suspend/Erase Resume
โ– 
Data# Polling and Toggle Bits
โ– 
Unlock Bypass Program command
โ€” Reduces overall programming time when issuing multiple
program command sequences
HARDWARE FEATURES
โ– 
Any combination of sectors can be erased
โ– 
Ready/Busy# output (RY/BY#)
โ– 
Hardware reset pin (RESET#)
โ– 
WP#/ACC input pin
โ€” Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
โ€” Acceleration (ACC) function accelerates program timing
โ– 
Sector protection
โ€” Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
โ€” Temporary Sector Unprotect allows changing data in
protected sectors in-system
SRAM Features
โ– 
Power dissipation
โ€” Operating: 2 mA typical
โ€” Standby: 0.5 ยตA typical
โ– 
CE1s# and CE2s Chip Select
โ– 
Power down features using CE1s# and CE2s
โ– 
Data retention supply voltage: 1.0 to 2.2 volt
โ– 
Byte data control: LB#s (DQ7โ€“DQ0), UB#s (DQ15โ€“DQ8)


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