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AM29BDS640GBC3WSI 데이터시트(PDF) 30 Page - Advanced Micro Devices |
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AM29BDS640GBC3WSI 데이터시트(HTML) 30 Page - Advanced Micro Devices |
30 / 77 page 28 Am29BDS640G 25903C2 May 9, 2006 Data Sheet Table 8. Programmable Wait State Settings Notes: 1. Upon power-up or hardware reset, the default setting is seven wait states. 2. RDY will default to being active with data when the Wait State Setting is set to a total initial access cycle of 2. 3. Assumes even address. It is recommended that the wait state command sequence be written, even if the default wait state value is desired, to ensure the device is set as expected. A hardware reset will set the wait state to the default setting. Reduced Wait-State Handshaking Option If the device is equipped with the reduced wait-state handshaking option, the host system should set address bits A14–A12 to 010 for a clock frequency of 40 MHz or to 011 for a clock frequency of 54 MHz for the system/device to execute at maximum speed. Table 9 describes the typical number of clock cycles (wait states) for various conditions. Table 9. Initial Access Cycles vs. Frequency Note: In the 8-, 16- and 32-word burst read modes, the address pointer does not cross 64-word boundaries (addresses which are multiples of 3Fh). The autoselect function allows the host system to determine whether the flash device is enabled for reduced wait-state handshaking. See the “Autoselect Com- mand Sequence” section for more information. A14 A13 A12 Total Initial Access Cycles 0002 0013 0104 0115 1006 1017 System Frequency Range Even Initial Addr. Odd Initial Addr. Even Initial Addr. with Boundary Odd Initial Addr. with Boundary Device Speed Rating 6–11 MHz 2 2 3 4 40 MHz 12–23 MHz 2 3 4 5 24–33 MHz 3 4 5 6 34–40 MHz 4 5 6 7 40–47 MHz 4 5 6 7 54 MHz 48–54 MHz 5 6 7 8 |
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