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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM41PDS3224DB11IS 데이터시트(PDF) 26 Page - Advanced Micro Devices |
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AM41PDS3224DB11IS 데이터시트(HTML) 26 Page - Advanced Micro Devices |
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26 / 59 page  May 13, 2002 Am41PDS3224D 25 P R E L IMINARY When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Flash Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset im- mediately terminates the erase operation. If that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase opera- tion. Refer to the Flash Erase and Program Opera- tions tables in the AC Characteristics section for parameters, and Figure 20 section for timing dia- grams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 10 shows the ad- dress and data requirements for the sector erase com- mand sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase ad dres s and c omma nd foll owing the ex cee ded time-out may or may not be accepted. It is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than S ect or Erase or Erase Su spen d du ring t h e time-out period resets the device to the read mode. The system must rewrite the command se- quence and any additional addresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing sector. Refer to the Flash Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase opera- tion. Refer to the Flash Erase and Program Opera- tions tables in the AC Characteristics section for parameters, and Figure 20 section for timing dia- grams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written dur- ing the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a max- imum of 20 µs to suspend the erase operation. How- ever, when the Erase Suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The sys- tem can read data from or program data to any sector not selected for erasure. (The device “erase sus- pends” all sectors selected for erasure.) Note that un- lock bypass programming is not allowed when the device is erase-suspended. Reading at any address within erase-suspended sec- tors produces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to de ter m i ne i f a s e c t or i s ac ti v e l y er as i ng or i s |
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