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AM42BDS640AG ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - Advanced Micro Devices

๋ถ€ํ’ˆ๋ช… AM42BDS640AG
์ƒ์„ธ๋‚ด์šฉ  64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
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์ œ์กฐ์‚ฌ  AMD [Advanced Micro Devices]
ํ™ˆํŽ˜์ด์ง€  http://www.amd.com
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AM42BDS640AG ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 2 Page - Advanced Micro Devices

 
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PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 26445
Rev: B Amendment/0
Issue Date: November 1, 2002
Refer to AMDโ€™s Website (www.amd.com) for the latest information.
Am42BDS640AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
โ–  Power supply voltage of 1.65 to 1.95 volt
โ–  High performance
โ€” Access time as fast as 70 ns
โ–  Package
โ€” 93-Ball FBGA
โ–  Operating Temperature
โ€” โ€“40ยฐC to +85ยฐC
Flash Memory Features
ARCHITECTURAL ADVANTAGES
โ–  Single 1.8 volt read, program and erase (1.65 to 1.95 volt)
โ–  Manufactured on 0.17 ยตm process technology
โ–  Simultaneous Read/Write operation
โ€” Data can be continuously read from one bank while
executing erase/program functions in other bank
โ€” Zero latency between read and write operations
โ€” Four bank architecture: 16Mb/16Mb/16Mb/16Mb
โ–  Programmable Burst Interface
โ€” 2 Modes of Burst Read Operation
โ€” Linear Burst: 8, 16, and 32 words with wrap-around
โ€” Continuous Sequential Burst
โ–  Sector Architecture
โ€” Eight 8 Kword sectors and one hundred twenty-six 32
Kword sectors
โ€” Banks A and D each contain four 8 Kword sectors and
thirty-one 32 Kword sectors; Banks B and C each contain
thirty-two 32 Kword sectors
โ€” Eight 8 Kword boot sectors, four at the top of the address
range, and four at the bottom of the address range
โ–  Minimum 1 million erase cycle guarantee per sector
โ–  20-year data retention at 125ยฐC
PERFORMANCE CHARCTERISTICS
โ–  Read access times at 54/40 MHz
โ€” Burst access times of 13.5/20 ns @ 30 pF at industrial
temperature range
โ€” Asynchronous random access times of 70 ns (at 30 pF)
โ€” Synchronous latency of 87.5/95 ns
โ–  Power dissipation (typical values, C
L = 30 pF)
โ€” Burst Mode Read: 10 mA
โ€” Simultaneous Operation: 25 mA
โ€” Program/Erase: 15 mA
โ€” Standby mode: 0.2 ยตA
HARDWARE FEATURES
โ–  Software command sector locking
โ–  Handshaking: host monitors operations via RDY output
โ–  Hardware reset input (RESET#)
โ–  WP# input
โ€” Write protect (WP#) function protects sectors 0, 1 (bottom
boot) or sectors 132 and 133 (top boot), regardless of sector
protect status
โ–  ACC input: Acceleration function reduces programming
time; all sectors locked when ACC = V
IL
โ–  CMOS compatible inputs, CMOS compatible outputs
โ–  Low V
CC write inhibit
SOFTWARE FEATURES
โ–  Supports Common Flash Memory Interface (CFI)
โ–  Software command set compatible with JEDEC 42.4
standards
โ–  Data# Polling and toggle bits
โ–  Erase Suspend/Resume
โ€” Suspends or resumes an erase operation in one sector to
read data from, or program data to, other sectors
โ–  Unlock Bypass Program command
โ€” Reduces overall programming time when issuing multiple
program command sequences
SRAM Features
โ–  Power dissipation
โ€” Operating: 3 mA maximum
โ€” Standby: 15 ยตA maximum
โ–  CE1s# and CE2s Chip Select
โ–  Power down features using CE1s# and CE2s
โ–  Data retention supply voltage: 1.0 to 2.2 volt
โ–  Byte data control: LB#s (DQ7โ€“DQ0), UB#s (DQ15โ€“DQ8)


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