AD9271BSVZ-25 datasheet(9/58 Pages) AD

부품명	AD9271BSVZ-25

상세설명	Octal LNA/VGA/AAF/ADC and Crosspoint Switch

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Preliminary Technical Data

AD9271

Rev. PrA | Page 9 of 58

SWITCHING SPECIFICATIONS

AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 m V p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless

otherwise noted.

Table 3.

Parameter1

Temp

Min

Typ

Max

Unit

CLOCK2

Maximum Clock Rate

Full

50

MSPS

Minimum Clock Rate

Full

10

MSPS

Clock Pulse Width High (tEH)

Full

10.0

ns

Clock Pulse Width Low (tEL)

Full

10.0

ns

OUTPUT PARAMETERS2, 3

Propagation Delay (tPD)

Full

1.5

2.3

3.1

ns

Rise Time (tR) (20% to 80%)

Full

300

ps

Fall Time (tF) (20% to 80%)

Full

300

ps

FCO Propagation Delay (tFCO)

Full

1.5

2.3

3.1

ns

DCO Propagation Delay (tCPD)4

Full

tFCO +

(tSAMPLE/24)

ns

DCO to Data Delay (tDATA)4

Full

(tSAMPLE/24) − 300

(tSAMPLE/24)

(tSAMPLE/24) + 300

ps

DCO to FCO Delay (tFRAME)4

Full

(tSAMPLE/24) − 300

(tSAMPLE/24)

(tSAMPLE/24) + 300

ps

Data-to-Data Skew

(tDATA-MAX − tDATA-MIN)

Full

±50

±200

ps

Wake-Up Time (Standby)

25°C

600

ns

Wake-Up Time (Power-Down)

25°C

375

μs

Pipeline Latency

Full

8

CLK

cycles

APERTURE

Aperture Uncertainty (Jitter)

25°C

<1

ps rms

1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.

2 Can be adjusted via the SPI interface.

3 Measurements were made using a part soldered to FR4 material.

4 tSAMPLE/24 is based on the number of bits divided by 2, because the delays are based on half duty cycles.

유사한 부품 번호 - AD9271BSVZ-25

제조업체	부품명	데이터시트	상세설명
Analog Devices	AD9271BSVZ-25	1Mb / 61P	Octal LNA/VGA/AAF/ADC and Crosspoint Switch

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유사한 설명 - AD9271BSVZ-25

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