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AD9271-50EBZ 데이터시트(PDF) 8 Page - Analog Devices

부품명 AD9271-50EBZ
상세설명  Octal LNA/VGA/AAF/ADC and Crosspoint Switch
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AD9271
Preliminary Technical Data
Rev. PrA | Page 8 of 58
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, CWVDD = 3.3 V, 400 m V p-p differential input, 1.0 V internal ADC reference, AIN = −0.5 dBFS, unless
otherwise noted.
Table 2.
Parameter1
Temperature
Min
Typ
Max
Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
Differential Input Voltage2
Full
250
mV p-p
Input Common-Mode Voltage
Full
1.2
V
Input Resistance (Differential)
25°C
20
Input Capacitance
25°C
1.5
pF
LOGIC INPUTS (PDWN, STBY, SCLK)
Logic 1 Voltage
Full
1.2
3.6
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
30
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (CSB)
Logic 1 Voltage
Full
1.2
3.6
V
Logic 0 Voltage
Full
0.3
V
Input Resistance
25°C
70
Input Capacitance
25°C
0.5
pF
LOGIC INPUT (SDIO)
Logic 1 Voltage
Full
1.2
DRVDD + 0.3
V
Logic 0 Voltage
Full
0
0.3
V
Input Resistance
25°C
30
Input Capacitance
25°C
2
pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Full
1.79
V
Logic 0 Voltage (IOL = 50 μA)
Full
0.05
V
DIGITAL OUTPUTS (D+, D−), (ANSI-644)1
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
247
454
mV
Output Offset Voltage (VOS)
Full
1.125
1.375
V
Output Coding (Default)
Offset binary
DIGITAL OUTPUTS (D+, D−),
(Low Power, Reduced Signal Option)1
Logic Compliance
LVDS
Differential Output Voltage (VOD)
Full
150
250
mV
Output Offset Voltage (VOS)
Full
1.10
1.30
V
Output Coding (Default)
Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.


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