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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AM50DL128CG 데이터시트(PDF) 29 Page - Advanced Micro Devices |
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AM50DL128CG 데이터시트(HTML) 29 Page - Advanced Micro Devices |
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29 / 63 page  28 Am50DL128CG November 7, 2002 P R E L I M I NARY Figure 4. Program Operation Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any con- trols or timings during these operations. Table 11 shows the address and data requirements for the chip erase command sequence. When the Embedded Erase algorithm is complete, that bank returns to the read mode and addresses are no longer latched. The system can determine the sta- tus of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Flash Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program op- eration is in progress. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the chip erase command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Figure 5 illustrates the algorithm for the erase opera- tion. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 11 shows the ad- dress and data requirements for the sector erase com- mand sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. After the command sequence is written, a sector erase time-out of 80 µs occurs. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 80 µs, otherwise erasure may begin. Any sector erase a ddre ss a nd command fo llo wing the exce ede d time-out may or may not be accepted. It is recom- mended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than S e c t or E r as e or E r ase S u spe n d du ring th e time-out period resets that bank to the read mode. Note that the SecSi Sector, autoselect, and CFI func- tions are unavailable when a program operation is in progress. The system must rewrite the command se- quence and any additional addresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the bank returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing bank. The system can de- START Write Program Command Sequence Data Poll from System Verify Data? No Yes Last Address? No Yes Programming Completed Increment Address Embedded Program algorithm in progress Note: See Table 11 for program command sequence. |
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