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AM29BDS320GTC8VMI 데이터시트(PDF) 14 Page - SPANSION |
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AM29BDS320GTC8VMI 데이터시트(HTML) 14 Page - SPANSION |
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14 / 74 page  12 Am29BDS320G 27243B1 October 1, 2003 Prelimin ary Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is com- posed of latches that store the commands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and con- trol levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Device Bus Operations Legend: L = Logic 0, H = Logic 1, X = Don’t Care, S = Stable Logic 0 or 1 but no transitions. Note: Default active edge of CLK is the rising edge. Enhanced VersatileIO™ (VIO) Control The Enhanced VersatileIO (VIO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data and address inputs to the same voltage level that is asserted on the VIO pin. The device is available with either 1.65–1.95 or 2.7–3.15 VIO. This allows the device to operate in 1.8 V or 3 V system environments as required. For example, a VIO of 2.7 – 3.15 volts allows for I/O at the 3 volt level, driving and receiving signals to and from other 3 V devices on the same bus. Requirements for Asynchronous Read Operation (Non-Burst) To read data from the memory array, the system must first assert a valid address on A20–A0, while driving AVD# and CE# to VIL. WE# should remain at VIH. The rising edge of AVD# latches the address. The data will appear on DQ15–DQ0. Operation CE# OE# WE# A20–0 DQ15–0 RESET# CLK (See Note) AVD# Asynchronous Read - Addresses Latched L L H Addr In I/O H X Asynchronous Read - Addresses Steady State L L H Addr In I/O H X L Asynchronous Write L H L Addr In I/O H L L Synchronous Write L H L Addr In I/O H Standby (CE#) H X X HIGH Z HIGH Z H X X Hardware Reset X X X HIGH Z HIGH Z L X X Burst Read Operations Load Starting Burst Address L X H Addr In X H Advance Burst to next address with appropriate Data presented on the Data Bus LL H HIGH Z Burst Data Out HH Terminate current Burst read cycle H X H HIGH Z HIGH Z H X Terminate current Burst read cycle via RESET# X X H HIGH Z HIGH Z L X X Terminate current Burst read cycle and start new Burst read cycle LX H HIGH Z I/O H |
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