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AM29BDS320GBC8VMI 데이터시트(PDF) 51 Page - SPANSION |
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AM29BDS320GBC8VMI 데이터시트(HTML) 51 Page - SPANSION |
51 / 74 page October 1, 2003 27243B1 Am29BDS320G 49 Prelimin ary AC Characteristics Notes: 1. Figure shows total number of wait states set to four cycles. The total number of wait states can be programmed from two cycles to seven cycles. Clock is set for active falling edge. 2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY. 3. The device is in synchronous mode. 4. In the Burst Mode Configuration Register, A17 = 0. Figure 12. CLK Synchronous Burst Mode Read (Falling Active Clock) Da Da + 1 Da + n OE# DQ15-DQ0 A20-A0 Aa AVD# RDY CLK CE# tCES tACS tAVC tAVD tACH tOE tOEZ tCEZ tIACC tACC tBDH 4 cycles for initial access shown. tRACC Hi-Z Hi-Z Hi-Z 12 3 4 5 tRDYS tBACC |
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