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AM29BDS320GBD4VMI ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 3 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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Publication Number 27243
Revision B Amendment 1 Issue Date October 1, 2003
PRELIMINARY
Am29BDS320G
32 Megabit (2 M x 16-Bit), 1.8 Volt-only
Simultaneous Read/Write, Burst Mode Flash Memory
Data Sheet
Distinctive Characteristics
Architectural Advantages
Single 1.8 volt read, program and erase (1.65 to
1.95 volt)
Manufactured on 0.17 ยตm process technology
Enhanced VersatileIOโ„ข (VIO) Feature
โ€” Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
โ€” 1.8V and 3V compatible I/O signals
Simultaneous Read/Write operation
โ€” Data can be continuously read from one bank while
executing erase/program functions in other bank
โ€” Zero latency between read and write operations
โ€” Four bank architecture: 8Mb/8Mb/8Mb/8Mb
Programmable Burst Interface
โ€” 2 Modes of Burst Read Operation
โ€” Linear Burst: 8, 16, and 32 words with wrap-around
โ€” Continuous Sequential Burst
Sector Architecture
โ€” Eight 8 Kword sectors and sixty-two 32 Kword
sectors
โ€” Banks A and D each contain four 8 Kword sectors and
fifteen 32 Kword sectors; Banks B and C each contain
sixteen 32 Kword sectors
โ€” Eight 8 Kword boot sectors, four at the top of the
address range, and four at the bottom of the address
range
Minimum 1 million erase cycle guarantee per
sector
20-year data retention at 125ยฐC
โ€” Reliable operation for the life of the system
64-ball FBGA package
Performance Charcteristics
Read access times at 54/40 MHz (at 30 pF)
โ€” Burst access times of 13.5/20 ns
โ€” Asynchronous random access times of 70 ns
โ€” Initial Synchronous access times as fast as 87.5/95 ns
Power dissipation (typical values, CL = 30 pF)
โ€” Burst Mode Read: 10 mA
โ€” Simultaneous Operation: 25 mA
โ€” Program/Erase: 15 mA
โ€”Standby mode: 0.2 ยตA
Hardware Features
Sector Protection
โ€” Software command sector locking
Reduced Wait-State Handshaking feature available
โ€” Provides host system with minimum possible latency
by monitoring RDY
Hardware reset input (RESET#)
โ€” Hardware method to reset the device for reading
array data
WP# input
โ€” Write protect (WP#) function protects sectors 0 and 1
(bottom boot), or sectors 68 and 69 (top boot),
regardless of sector protect status
ACC input: Acceleration function reduces
programming time; all sectors locked when ACC =
VIL
CMOS compatible inputs, CMOS compatible outputs
Low VCC write inhibit
Software Features
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC
42.4 standards
โ€” Backwards compatible with Am29F and Am29LV
families
Data# Polling and toggle bits
โ€” Provides a software method of detecting program
and erase operation completion
Erase Suspend/Resume
โ€” Suspends an erase operation to read data from, or
program data to, a sector that is not being erased,
then resumes the erase operation
Unlock Bypass Program command
โ€” Reduces overall programming time when issuing
multiple program command sequences


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