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AM29BDS320GBC4VMI ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 29 Page - SPANSION

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์ƒ์„ธ๋‚ด์šฉ  32 Megabit (2 M x 16-Bit), 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory
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October 1, 2003 27243B1
Am29BDS320G
27
Prelimin ary
Table 8. Programmable Wait State Settings
Notes:
1. Upon power-up or hardware reset, the default setting is seven wait states.
2. RDY will default to being active with data when the Wait State Setting is set to a
total initial access cycle of 2.
3. Assumes even address.
It is recommended that the wait state command sequence be written, even if the
default wait state value is desired, to ensure the device is set as expected. A
hardware reset will set the wait state to the default setting.
Reduced Wait-State Handshaking Option
If the device is equipped with the reduced wait-state handshaking option, the
host system should set address bits A14โ€“A12 to 010 for a clock frequency of 40
MHz or to 011 for a clock frequency of 54 MHz for the system/device to execute
at maximum speed.
Table 9 describes the typical number of clock cycles (wait states) for various
conditions.
Table 9. Initial Access Cycles vs. Frequency
Note: In the 8-, 16- and 32-word burst read modes, the address pointer does not
cross 64-word boundaries (3Fh, and addresses offset from 3Fh by a multiple of 64).
The autoselect function allows the host system to determine whether the flash
device is enabled for reduced wait-state handshaking. See the โ€œAutoselect Com-
mand Sequenceโ€ section for more information.
A14
A13
A12
Total Initial Access Cycles
00
0
2
00
1
3
01
0
4
01
1
5
10
0
6
10
1
7
System
Frequency
Range
Even
Initial
Addr.
Odd
Initial
Addr.
Even
Initial
Addr.
with
Boundary
Odd Initial
Addr.
with
Boundary
Device Speed
Rating
6โ€“11 MHz
2
2
3
4
40 MHz
12โ€“23 MHz
2
3
4
5
24โ€“33 MHz
3
4
5
6
34โ€“40 MHz
4
5
6
7
40โ€“47 MHz
4
5
6
7
54 MHz
48โ€“54 MHz
5
6
7
8


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