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AM29BDS320GBC4VMI 데이터시트(PDF) 31 Page - SPANSION |
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AM29BDS320GBC4VMI 데이터시트(HTML) 31 Page - SPANSION |
31 / 74 page October 1, 2003 27243B1 Am29BDS320G 29 Prelimin ary edge is active for all synchronous accesses. Address bit A17 determines this set- ting; “1” for rising active, “0” for falling active. RDY Configuration By default, the device is set so that the RDY pin will output VOH whenever there is valid data on the outputs. The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determines this setting; “1” for RDY active with data, “0” for RDY active one clock cycle before valid data. Configuration Register Table 12 shows the address bits that determine the configuration register settings for various device functions. Table 12. Burst Mode Configuration Register Note: Device will be in the default state upon power-up or hardware reset. Sector Lock/Unlock Command Sequence The sector lock/unlock command sequence allows the system to determine which sectors are protected from accidental writes. When the device is first powered up, all sectors are locked. To unlock a sector, the system must write the sector lock/ unlock command sequence. In the first and second cycles, the address must point to the bank that contains the sector(s) to be locked or unlocked. The first and second cycle data is 60h. In the third cycle, the address must point to the target sector, and A6 is used to specify a lock (A6 = VIL) or unlock (A6 = VIH) operation. The third cycle data is 60h. After the third cycle, the system can continue to lock or unlock additional sectors in the same bank or exit the sector lock/unlock se- quence by writing the reset command (F0h). It is not possible to read from the bank selected for sector lock/unlock operations. To enable such read operations, write the reset command. Note that the last two outermost boot sectors can be locked by taking the WP# signal to VIL. Address Bit Function Settings (Binary) A19 Set Device Read Mode 0 = Synchronous Read (Burst Mode) Enabled 1 = Asynchronous Mode (default) A18 RDY 0 = RDY active one clock cycle before data 1 = RDY active with data (default) A17 Clock 0 = Burst starts and data is output on the falling edge of CLK 1 = Burst starts and data is output on the rising edge of CLK (default) A16 Burst Read Mode 00 = Continuous (default) 01 = 8-word linear with wrap around 10 = 16-word linear with wrap around 11 = 32-word linear with wrap around A15 A14 Programmable Wait State 000 = Data is valid on the 2nd active CLK edge after AVD# transition to VIH 001 = Data is valid on the 3rd active CLK edge after AVD# transition to VIH 010 = Data is valid on the 4th active CLK edge after AVD# transition to VIH 011 = Data is valid on the 5th active CLK edge after AVD# transition to VIH 100 = Data is valid on the 6th active CLK edge after AVD# transition to VIH 101 = Data is valid on the 7th active CLK edge after AVD# transition to VIH (default) A13 A12 |
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