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AM42BDS6408H ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 3 Page - SPANSION

๋ถ€ํ’ˆ๋ช… AM42BDS6408H
์ƒ์„ธ๋‚ด์šฉ  CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory, and 8 Mbit (512 K x 16-Bit) SRAM
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์ œ์กฐ์‚ฌ  SPANSION [SPANSION]
ํ™ˆํŽ˜์ด์ง€  http://www.spansion.com
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ADVANCE INFORMATION
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. Do not design in this product without contacting the factory. AMD re-
serves the right to change or discontinue work on this proposed product without notice.
Publication# 30491
Rev: A Amendment:+3
Issue Date: October 23, 2003
Refer to AMDโ€™s Website (www.amd.com) for the latest information.
Am42BDS6408H
Am29BDS640H 64 Megabit (4 M x 16-Bit)
Stacked MultiChip Package (MCP) Flash Memory and SRAM
CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash
Memory, and 8 Mbit (512 K x 16-Bit) SRAM
FLASH DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
โ–  Single 1.8 volt read, program and erase (1.65 to 1.95
volt)
โ–  Manufactured on 0.13 ยตm process technology
โ–  VersatileIOโ„ข (VIO) Feature
โ€” Device generates data output voltages and tolerates
data input voltages as determined by the voltage on
the VIO pin
โ€” 1.8V compatible I/O signals
โ€” Contact factory for availability of 1.5V compatible I/O
signals
โ– 
Simultaneous Read/Write operation
โ€” Data can be continuously read from one bank while
executing erase/program functions in other bank
โ€” Zero latency between read and write operations
โ€” Four bank architecture: 8Mb/24Mb/24Mb/8Mb
โ– 
Programable Burst Interface
โ€” 2 Modes of Burst Read Operation
โ€” Linear Burst: 8, 16, and 32 words with
wrap-around
โ€” Continuous Sequential Burst
โ– 
SecSiTM (Secured Silicon) Sector region
โ€” Up to 128 words accessible through a command
sequence
โ€” Up to 64 factory-locked words
โ€” Up to 64 customer-lockable words
โ– 
Sector Architecture
โ€” Sixteen 4 Kword sectors and one hundred twenty-six
32 Kword sectors
โ€” Banks A and D each contain eight 4 Kword sectors
and fifteen 32 Kword sectors; Banks B and C each
contain forty-eight 32 Kword sectors
โ€” Sixteen 4 Kword boot sectors: eight at the top of the
address range and eight at the bottom of the address
range
โ–  Minimum 1 million erase cycle guarantee per sector
โ–  20-year data retention at 125ยฐC
โ€” Reliable operation for the life of the system
โ–  89-ball FBGA package
PERFORMANCE CHARCTERISTICS
โ– 
Read access times at 66/54 MHz (CL=30 pF)
โ€” Burst access times of 11/13.5 ns at industrial
temperature range
โ€” Synchronous latency of 56/69 ns
โ€” Asynchronous random access times of 45/50/55 ns
โ–  Power dissipation (typical values, CL = 30 pF)
โ€” Burst Mode Read: 10 mA
โ€” Simultaneous Operation: 25 mA
โ€” Program/Erase: 15 mA
โ€” Standby mode: 0.2 ยตA
HARDWARE FEATURES
โ–  Handshaking feature
โ€” Provides host system with minimum possible latency
by monitoring RDY
โ€” Reduced Wait-state handshaking option further
reduces initial access cycles required for burst
accesses beginning on even addresses
โ–  Hardware reset input (RESET#)
โ€” Hardware method to reset the device for reading array
data
โ–  WP# input
โ€” Write protect (WP#) function allows protection of the
four highest and four lowest 4 kWord boot sectors,
regardless of sector protect status
โ–  Persistent Sector Protection
โ€” A command sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector
โ€” Sectors can be locked and unlocked in-system at VCC
level
โ–  Password Sector Protection
โ€” A sophisticated sector protection method to lock
combinations of individual sectors and sector groups
to prevent program or erase operations within that
sector using a user-defined 64-bit password
โ–  ACC input: Acceleration function reduces
programming time; all sectors locked when ACC =
VIL


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