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AM42BDS6408HE3I 데이터시트(PDF) 74 Page - SPANSION |
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74 / 90 page 72 Am42BDS6408H October 23, 2003 A D VA NCE I N FO RM ATIO N AC CHARACTERISTICS Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, and Data# Polling will output true data. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode. Figure 37. Data# Polling Timings (During Embedded Algorithm) Notes: 1. Status reads in figure are shown as asynchronous. 2. VA = Valid Address. Two read cycles are required to determine status. When the Embedded Algorithm operation is complete, the toggle bits will stop toggling. 3. While in Asynchronous mode, RDY will be low while the device is in embedded erase or programming mode. Figure 38. Toggle Bit Timings (During Embedded Algorithm) WE# CE# OE# tOE Addresses AVD# tOEH tCE tCH tOEZ tCEZ Status Data Status Data tACC VA VA Data WE# CE# OE# tOE Addresses AVD# tOEH tCE tCH tOEZ tCEZ Status Data Status Data tACC VA VA Data |
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