전자부품 데이터시트 검색엔진 |
|
GT3200-JN 데이터시트(PDF) 11 Page - SMSC Corporation |
|
GT3200-JN 데이터시트(HTML) 11 Page - SMSC Corporation |
11 / 48 page USB2.0 PHY IC Datasheet SMSC GT3200, SMSC USB3250 11 Revision 1.5 (03-24-06) DATASHEET Table 4.2 Data Interface Signals NAME DIRECTION ACTIVE LEVEL DESCRIPTION DATA[15:0] Bidir N/A DATA BUS. 16-BIT BIDIRECTIONAL MODE. TXVALID RXVALID VALIDH DATA[15:0] 0 0 X Not used 0 1 0 DATA[7:0] output is valid for receive VALIDH is an output 0 1 1 DATA[15:0] output is valid for receive VALIDH is an output 1 X 0 DATA[7:0] input is valid for transmit VALIDH is an input 1 X 1 DATA[15:0] input is valid for transmit VALIDH is an input DATA BUS. 8-BIT UNIDIRECTIONAL MODE. TXVALID RXVALID DATA[15:0] 00 Not used 0 1 DATA[15:8] output is valid for receive 1 X DATA[7:0] input is valid for transmit TXVALID Input High Transmit Valid. Indicates that the TXDATA bus is valid for transmit. The assertion of TXVALID initiates the transmission of SYNC on the USB bus. The negation of TXVALID initiates EOP on the USB. Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT) must not be changed on the de-assertion or assertion of TXVALID. The PHY must be in a quiescent state when these inputs are changed. TXREADY Output High Transmit Data Ready. If TXVALID is asserted, the SIE must always have data available for clocking into the TX Holding Register on the rising edge of CLKOUT. TXREADY is an acknowledgement to the SIE that the transceiver has clocked the data from the bus and is ready for the next transfer on the bus. If TXVALID is negated, TXREADY can be ignored by the SIE. VALIDH Bidir N/A Transmit/Receive High Data Bit Valid (used in 16-bit mode only). When TXVALID = 1, the 16-bit data bus direction is changed to inputs, and VALIDH is an input. If VALIDH is asserted, DATA[15:0] is valid for transmission. If deasserted, only DATA[7:0] is valid for transmission. The DATA bus is driven by the SIE. When TXVALID = 0 and RXVALID = 1, the 16-bit data bus direction is changed to outputs, and VALIDH is an output. If VALIDH is asserted, the DATA[15:0] outputs are valid for receive. If deasseted, only DATA[7:0] is valid for receive. The DATA bus is read by the SIE. RXVALID Output High Receive Data Valid. Indicates that the RXDATA bus has received valid data. The Receive Data Holding Register is full and ready to be unloaded. The SIE is expected to latch the RXDATA bus on the rising edge of CLKOUT. RXACTIVE Output High Receive Active. Indicates that the receive state machine has detected Start of Packet and is active. RXERROR Output High Receive Error. 0: Indicates no error. 1: Indicates a receive error has been detected. This output is clocked with the same timing as the RXDATA lines and can occur at anytime during a transfer. |
유사한 부품 번호 - GT3200-JN |
|
유사한 설명 - GT3200-JN |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |