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LAN9115 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 40 Page - SMSC Corporation

๋ถ€ํ’ˆ๋ช… LAN9115
์ƒ์„ธ๋‚ด์šฉ  Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
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LAN9115 ๋ฐ์ดํ„ฐ์‹œํŠธ(HTML) 40 Page - SMSC Corporation

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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
40
SMSC LAN9115
DATASHEET
3.10.2.3
Power Managment Event Indicators
Figure 3.11 is a simplified block diagram of the logic that controls the external PME, and internal
pme_interrupt signals. The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS
register, which, if enabled, will generate a host interrupt upon detection of a power management event.
The PME_INT status bit in INT_STS will remain set until the internal pme_interrupt signal is cleared
by clearing the WUPS bits, or by clearing the corresponding WOL_EN or ED_EN bit. After clearing the
internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a โ€˜1โ€™ to this bit in the
INT_STS register. It should be noted that the LAN9115 can generate a host interrupt regardless of the
state of the PME_EN bit, or the external PME signal.
The external PME signal can be setup for pulsed, or static operation. When the PME_IND bit in the
PMT_CTRL register is set to a โ€˜1โ€™, the external PME signal will be driven active for 50ms upon
detection of a wake-up event. When the PME_IND bit is cleared, the PME signal will be driven
continously upon detection of a wake-up event. The PME signal is deactivated by clearing the WUPS
bits, or by clearing the corresponding WOL_EN or ED_EN bit. The PME signal can also be deactivated
by clearing the PME_EN bit.
Figure 3.11 PME and PME_INT Signal Generation
3.10.3
Internal PHY Power-Down modes
There are 2 power-down modes for the internal Phy:
3.10.3.1
General Power-Down
This power-down is controlled by register 0, bit 11. In this mode the internal PHY, except the
management interface, is powered-down and stays in that condition as long as Phy register bit 0.11 is
HIGH. When bit 0.11 is cleared, the PHY powers up and is automatically reset. Please refer to Section
5.5.1, "Basic Control Register," on page 107 for additional information on this register.
PME
ED_EN
WOL_EN
50ms
PME_EN
PME_IND
PME_POL
PME_TYPE
LOGIC
WUEN
MPEN
phy_int
WUPS
WUPS
WUFR
MPR
Denotes a level-triggered "sticky" status bit
PME_INT_EN
PME_INT
IRQ_EN
IRQ
Other System
Interrupts


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