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LAN9115 데이터시트(HTML) 80 Page - SMSC Corporation

부품명 LAN9115
상세내용  Highly Efficient Single- Chip 10/100 Non-PCI Ethernet Controller
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제조사  SMSC [SMSC Corporation]
홈페이지  http://www.smsc.com
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LAN9115 데이터시트(HTML) 80 Page - SMSC Corporation

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Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller
Datasheet
Revision 1.1 (05-17-05)
80
SMSC LAN9115
DATASHEET
5.3.9
HW_CFG—Hardware Configuration Register
This register controls the hardware configuration of the LAN9115 Ethernet Controller
2
TX Status Allow Overrun (TXSAO). When this bit is cleared, data
transmission is suspended if the TX Status FIFO becomes full. Setting this
bit high allows the transmitter to continue operation with a full TX Status
FIFO.
Note:
This bit does not affect the operation of the TX Status FIFO Full
interrupt.
R/W
0
1
Transmitter Enable (TX_ON). When this bit is set (1), the transmitter is
enabled. Any data in the TX FIFO will be sent. This bit is cleared
automatically when STOP_TX is set and the transmitter is halted.
R/W
0
0
Stop Transmitter (STOP_TX). When this bit is set (1), the transmitter will
finish the current frame, and will then stop transmitting. When the transmitter
has stopped this bit will clear. All writes to this bit are ignored while this bit
is high.
SC
0
Offset:
74h
Size:
32 bits
BITS
DESCRIPTION
TYPE
DEFAULT
31-22
Reserved
RO
-
21
Transmit Threshold Mode (TTM). This bit is used to control the transmit
threshold the MIL uses as shown in the two tables in the TR field of this
register. This bit is ignored when the SF bit is set (1).
This bit should be set to '1' when operating in 10Mbps mode, and cleared
to '0' when operating in 100Mbps mode if the SF bit cleared.
R/W
0
20
Store and Forward (SF). When set, this bit instructs the MIL to store a
frame of transmit data in the MIL buffer before forwarding to its final
destination.
If this bit is set, the MIL buffers the entire frame before transmitting. TTM
and TR (see bits 21,13, and 12) are treated as Don’t Cares once the SF
mode is selected.
If this bit is reset, the MAC initiates transmission before it receives the entire
frame from the HBI (Host Bus Interface). TTM and TR (see bit 21,13, and
12) determine when the MIL initiates the transmission. If the host cannot
keep up with the MAC transmitting the Ethernet Packet, there is a risk of an
Underrun Error.
R/W
0
BITS
DESCRIPTION
TYPE
DEFAULT


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