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LAN9115-MD 데이터시트(PDF) 79 Page - SMSC Corporation |
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LAN9115-MD 데이터시트(HTML) 79 Page - SMSC Corporation |
79 / 131 page Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller Datasheet SMSC LAN9115 79 Revision 1.1 (05-17-05) DATASHEET 5.3.8 TX_CFG—Transmit Configuration Register This register controls the transmit functions on the LAN9115 Ethernet Controller. 15 Force RX Discard (RX_DUMP). This self-clearing bit clears the RX data and status FIFOs of all pending data. When a ‘1’ is written, the RX data and status pointers are cleared to zero. Note: Please refer to section “Force Receiver Discard (Receiver Dump)” on page 59 for a detailed description regarding the use of RX_DUMP. SC 0 14-13 Reserved RO - 12-8 RX Data Offset (RXDOFF). This field controls the offset value, in bytes, that is added to the beginning of an RX data packet. The start of the valid data will be shifted by the number of bytes specified in this field. An offset of 0-31 bytes is a valid number of offset bytes. Note: The two LSBs of this field (D[9:8]) must not be modified while the RX is running. The receiver must be halted, and all data purged before these two bits can be modified. The upper three bits (DWORD offset) may be modified while the receiver is running. Modifications to the upper bits will take affect on the next DWORD read. R/W 00000 7-0 Reserved RO - Table 5.2 RX Alignment Bit Definitions [31] [30] End Alignment 0 0 4-byte alignment 0 1 16-byte alignment 1 0 32-byte alignment 11 Reserved Offset: 70h Size: 32 bits BITS DESCRIPTION TYPE DEFAULT 31-16 Reserved. RO - 15 Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX status pointers are cleared to zero. SC 0 14 Force TX Data Discard (TXD_DUMP). This self-clearing bit clears the TX data FIFO of all pending data. When a ‘1’ is written, the TX data pointers are cleared to zero. SC 0 13-3 Reserved RO - BITS DESCRIPTION TYPE DEFAULT |
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