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74ABT373CMSA 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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74ABT373CMSA 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
2 / 13 page ©1993 Fairchild Semiconductor Corporation www.fairchildsemi.com 74ABT373 Rev. 1.4 2 Functional Description The ABT373 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable (OE) input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = HIGH Impedance State Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Inputs Output LE OE Dn On HLH H HL L L LL X On (no change) XHX Z |
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