©1988 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74AC573, 74ACT573 Rev. 1.5

2

Logic Symbols

Connection Diagram

Pin Descriptions

Truth Table

H

= HIGH Voltage

L

= LOW Voltage

Z

= High Impedance

X

= Immaterial

Latch Enable

Functional Description

The 74AC573 and 74ACT573 contain eight D-type

latches with 3-STATE output buffers. When the Latch

the latches. In this condition the latches are transparent,

i.e., a latch output will change state each time its D-type

input changes. When LE is LOW the latches store the

information that was present on the D-type inputs a

setup time preceding the HIGH-to-LOW transition of LE.

The 3-STATE buffers are controlled by the Output

Enable (OE) input. When OE is LOW, the buffers are

enabled. When OE is HIGH the buffers are in the high

impedance mode but this does not interfere with entering

new data into the latches.

IEEE/IEC

Pin Names

Description

Data Inputs

LE

Latch Enable Input

OE

3-STATE Output Enable Input

3-STATE Latch Outputs

Inputs

Outputs

OE

LE

D

LH

H

H

LH

L

L

LL

X

HX

X

Z