전자부품 데이터시트 검색엔진 |
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74F194SC 데이터시트(PDF) 2 Page - Fairchild Semiconductor |
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74F194SC 데이터시트(HTML) 2 Page - Fairchild Semiconductor |
2 / 6 page www.fairchildsemi.com 2 Unit Loading/Fan Out Functional Description The 74F194 contains four edge-triggered D-type flip-flops and the necessary interstage logic to synchronously per- form shift right, shift left, parallel load and hold operations. Signals applied to the Select (S0, S1) inputs determine the type of operation, as shown in the Mode Select Table. Sig- nals on the Select, Parallel data (P0–P3) and Serial data (DSR, DSL) inputs can change when the clock is in either state, provided only that the recommended setup and hold times, with respect to the clock rising edge, are observed. A LOW signal on Master Reset (MR) overrides all other inputs and forces the outputs LOW. Mode Select Table H (h) = HIGH Voltage Level L (l) = LOW Voltage Level pn (qn) = Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to-HIGH clock transition. X = Immaterial Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Pin Names Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL S0, S1 Mode Control Inputs 1.0/1.0 20 µA/−0.6 mA P0–P3 Parallel Data Inputs 1.0/1.0 20 µA/−0.6 mA DSR Serial Data Input (Shift Right) 1.0/1.0 20 µA/−0.6 mA DSL Serial Data Input (Shift Left) 1.0/1.0 20 µA/−0.6 mA CP Clock Pulse Input (Active Rising Edge) 1.0/1.0 20 µA/−0.6 mA MR Asynchronous Master Reset Input (Active LOW) 1.0/1.0 20 µA/−0.6 mA Q0–Q3 Parallel Outputs 50/33.3 −1 mA/20 mA Operating Inputs Outputs Mode MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 Reset L X X X X X L L L L Hold H l l X X X q0 q1 q2 q3 Shift Left H h l X l X q1 q2 q3 L Hh l X h X q1 q2 q3 H Shift Right H l h l X X L q0 q1 q2 Hlh h X X H q0 q1 q2 Parallel Load H h h X X pn p0 p1 p2 p3 |
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