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2

Unit Loading/Fan Out

Functional Description

This device contains two identical 4-input multiplexers with

3-STATE outputs. They select two bits from four sources

inputs which, when HIGH, force the outputs to a high

impedance (High Z) state. This device is the logic imple-

mentation of a 2-pole, 4-position switch, where the position

of the switch is determined by the logic levels supplied to

the two select inputs. The logic equations for the outputs

are shown below:

If the outputs of 3-STATE devices are tied together, all but

one device must be in the high impedance state to avoid

high currents that would exceed the maximum ratings.

Designers should ensure that Output Enable signals to

3-STATE devices whose outputs are tied together are

designed so that there is no overlap.

Truth Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Immaterial

Z

= High Impedance

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

Side A Data Inputs

1.0/1.0

20

µA/−0.6 mA

Side B Data Inputs

1.0/1.0

20

µA/−0.6 mA

Common Select Inputs

1.0/1.0

20

µA/−0.6 mA

Side A Output Enable Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

Side B Output Enable Input (Active LOW)

1.0/1.0

20

µA/−0.6 mA

3-STATE Outputs

150/40(33.3)

−3 mA/24 mA (20 mA)

Select

Data Inputs

Output

Output

Inputs

Enable

OE

Z

XX

XXX

X

H

Z

LL

L

X

X

X

L

L

LL

H

X

X

X

L

H

HL

X

L

X

X

L

L

HL

X

H

X

X

L

H

LH

X

X

L

X

L

L

LH

X

X

H

X

L

H

H

H

XXX

L

L

L

H

H

XXX

H

L

H