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AM49DL6408H85FS 데이터시트(PDF) 13 Page - SPANSION

부품명 AM49DL6408H85FS
상세설명  64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 8 Mbit (512 K x 16-Bit)
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March 12, 2004
Am49DL6408H
11
ADV ANCE
I N FO RMAT I O N
I
CC3f in the table represents the standby current spec-
ification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC +
30 ns. The automatic sleep mode is independent of
the CE#f, WE#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC5f in the table represents the automatic sleep mode
current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
RP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS±0.3 V, the device
draws CMOS standby current (I
CC4f). If RESET# is
held at V
IL but not within VSS±0.3 V, the standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY (during Embedded Algorithms). The
system can th us monito r RY/BY# to de termin e
whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not ex-
ecuting (RY/BY# pin is “1”), the reset operation is com-
pleted within a time of t
READY (not during Embedded
Algorithms). The system can read data t
RH after the
RESET# pin returns to V
IH.
Refer to the Flash DC characteristics tables for RE-
SET# parameters and to Figure 16 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at V
IH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Table 2.
Am29DL640H Sector Architecture
Bank
Sector
Sector Address
A21–A12
Sector Size
(Kwords)
(x16)
Address Range
Bank 1
SA0
0000000000
4
00000h–00FFFh
SA1
0000000001
4
01000h–01FFFh
SA2
0000000010
4
02000h–02FFFh
SA3
0000000011
4
03000h–03FFFh
SA4
0000000100
4
04000h–04FFFh
SA5
0000000101
4
05000h–05FFFh
SA6
0000000110
4
06000h–06FFFh
SA7
0000000111
4
07000h–07FFFh
SA8
0000001xxx
32
08000h–0FFFFh
SA9
0000010xxx
32
10000h–17FFFh
SA10
0000011xxx
32
18000h–1FFFFh
SA11
0000100xxx
32
20000h–27FFFh
SA12
0000101xxx
32
28000h–2FFFFh
SA13
0000110xxx
32
30000h–37FFFh
SA14
0000111xxx
32
38000h–3FFFFh
SA15
0001000xxx
32
40000h–47FFFh
SA16
0001001xxx
32
48000h–4FFFFh
SA17
0001010xxx
32
50000h–57FFFh
SA18
0001011xxx
32
58000h–5FFFFh
SA19
0001100xxx
32
60000h–67FFFh
SA20
0001101xxx
32
68000h–6FFFFh
SA21
0001101xxx
32
70000h–77FFFh
SA22
0001111xxx
32
78000h–7FFFFh


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