© 2005 Fairchild Semiconductor Corporation

DS500227

www.fairchildsemi.com

January 2000

Revised June 2005

74VCXH162373

Low Voltage 16-Bit Transparent Latch with Bushold

and 26

: Series Resistors in Outputs

General Description

The VCXH162373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch enable

(LE) is HIGH. When LE is LOW, the data that meets the

setup time is latched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH, the out-

puts are in a high impedance state.

The VCXH162373 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

The VCXH162373 is also designed with 26

: series resis-

tors in the outputs. This design reduces line noise in appli-

cations such as memory address driver, clock drivers and

bus transceivers/transmitters.

The 74VCXH162373 is designed for low voltage (1.4V to

The 74VCXH162373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

s 3.6V tolerant control inputs and outputs

s Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

s 26

: series resistors in outputs

s Uses patented noise/EMI reduction circuitry

s Latch-up performance exceeds 300 mA

s ESD performance:

Human body model

! 2000V

Machine model

! 200V

Ordering Code:

Note 1: Use this Order Number to receive devices in Tape and Reel.

Logic Symbol

Pin Descriptions

Ordering Number

Package

Package Description

Number

74VCXH162373MTD

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TUBES]

74VCXH162373MTX

(Note 1)

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

[TAPE and REEL]

Pin Names

Description

Output Enable Input (Active LOW)

Latch Enable Input

Bushold Inputs

Outputs