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ISL24006IRZ 데이터시트(PDF) 8 Page - Intersil Corporation |
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ISL24006IRZ 데이터시트(HTML) 8 Page - Intersil Corporation |
8 / 10 page 8 FN6110.1 March 9, 2006 Data Byte Data Bytes are the input code data to the 8-bit DACs. Most significant bits are clocked in first. These data bytes determine the output voltages of the ISL24006. Ideal Transfer Function Example Given a typical voltage applied to VREFU_H and VREFU_L: Clock Oscillator The ISL24006 require an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn't be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labelled OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the OSC pin. In a two-chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. For transient load application, the external clock mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will default with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. Channel Outputs Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 50mV of the power rails (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5 Ω and 50 Ω). Each of the channels is updated on a continuous cycle. The time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. Power-On Sequencing At power-on, make sure that AVDD ≥ DVDD - 0.5V to prevent the ESD diode between AVDD and DVDD from driving too much current. If DVDD comes on first, leave AVDD floating. Do not ground AVDD. Power Dissipation With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125°C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. TABLE 4. b7 b6 b5 b4 b3 b2 b1 b0 10111 010 2 7 1 () 2 6 0 () 2 5 1 () 2 4 1 () 2 3 1 () 2 2 0 () 2 1 1 () 2 0 0 () × + × + × + × + × + × + × + × TABLE 5. BINARY INPUT DECIMAL VOUT1 (V) VOUT14 (V) 00000000 0 8.5 1 00000001 1 8.521484 1.021484 00000011 3 8.564453 1.064453 00000111 7 8.650391 1.150391 00001111 15 8.822266 1.322266 00011111 31 9.166016 1.666016 00111111 63 9.853516 2.353516 01111111 127 11.22852 3.728516 11111111 255 13.97852 6.478516 VREF U_H 14V = VREF U_L 8.5V = R 14V 8.5V – 256 ----------------------------- 21.5mV == VREF L_H 6.5V = VREF L_L 1V = R 6.5V 1V – 256 -------------------------- 21.5mV == ISL24006 |
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