전자부품 데이터시트 검색엔진 |
|
ISL59481IRZ 데이터시트(PDF) 9 Page - Intersil Corporation |
|
ISL59481IRZ 데이터시트(HTML) 9 Page - Intersil Corporation |
9 / 12 page 9 FN6208.3 December 22, 2006 If positive voltages are applied to the logic or analog video input pins before V+ is applied, current will flow through the internal ESD diodes to the V+ pin. The presence of large decoupling capacitors and the loading effect of other circuits connected to V+, can result in damaging currents through the ESD diodes and other active circuits within the device. Therefore, adequate current limiting on the digital and analog inputs is needed to prevent damage during the time the voltages on these inputs are more positive than V+. HIZ State Each internal 4:1 triple MUX-amp has a three-state output control pin (HIZ1 and HIZ2). Each has an internal pull-down resistor to set the output to the enabled state with no connection to the HIZ pin. The HIZ state is established within approximately 15ns by placing a logic high (>2V) on the HIZ pin. If the HIZ state is selected, the output is a high impedance 1.4M Ω with approximately 1.5pF in parallel with a 10μA bias current from the output. When more than one MUX shares a common output, the high impedance state loading effect is minimized over the maximum output voltage swing and maintains its high Z even in the presence of high slew rates. The supply current during this state is the same as the active state. EN and Power-down States The EN pin is active low. An internal pull-down resistor ensures the device will be active with no connection to the EN pin. The power-down state is established within approximately 80ns, if a logic high (>2V) is placed on the EN pin. In the power-down state, supply current is reduced significantly by shutting the three amplifiers off. The output presents a high impedance to the output pin, however, there is a risk that the disabled amplifier output can be back-driven at signal voltage levels exceeding ~2VP-P. Under this condition, large incoming slew rates can cause fault currents of tens of mA. Therefore, the parallel connection of multiple outputs is not recommended unless the application can tolerate the limited power-down output impedance. Limiting the Output Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than 50mA. Adequate thermal heat sinking of the parts is also required. PC Board Layout The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • The use of low inductance components, such as chip resistors and chip capacitors, is strongly recommended. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners. Use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces greater than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. High frequency performance may be degraded for traces greater than one inch, unless controlled impedance (50 Ω or 75Ω) strip lines or microstrips are used. • Match channel-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. • Maximize use of AC de-coupled PCB layers. All signal I/O lines should be routed over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Avoid vias in the signal I/O lines. • Use proper value and location of termination resistors. Termination resistors should be as close to the device as possible. • When testing, use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum. • A minimum of 2 power supply decoupling capacitors are recommended (1000pF, 0.01µF) as close to the devices as possible. Avoid vias between the cap and the device because vias add unwanted inductance. Larger caps can be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. • The NIC pins are placed on both sides of the input pins. These pins are not internally connected to the die. It is recommended these pins be tied to ground to minimize crosstalk. V+ V+ V- V- V+ V- V+ V- LOGIC CONTROL GND IN0 IN1 S0 OUT EXTERNAL CIRCUITS SCHOTTKY PROTECTION V+ V- POWER GND SIGNAL LOGIC V+ SUPPLY V- SUPPLY DE-COUPLING CAPS FIGURE 16. SCHOTTKY PROTECTION CIRCUIT ISL59481 |
유사한 부품 번호 - ISL59481IRZ |
|
유사한 설명 - ISL59481IRZ |
|
|
링크 URL |
개인정보취급방침 |
ALLDATASHEET.CO.KR |
ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |