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SN74AUP1G74DCTR 데이터시트(PDF) 2 Page - Texas Instruments |
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SN74AUP1G74DCTR 데이터시트(HTML) 2 Page - Texas Instruments |
2 / 17 page www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) AUP LVC AUP AUP LVC Static-Power Consumption ( µA) Dynamic-Power Consumption (pF) † Single, dual, and triple gates 3.3-V Logic† 3.3-V Logic† 0% 20% 40% 60% 80% 100% 0% 20% 40% 60% 80% 100% −0.5 0 0.5 1 1.5 2 2.5 3 3.5 0 5 10 15 20 25 30 35 40 45 Time − ns † AUP1G08 data at CL = 15 pF Output Input Switching Characteristics at 25 MHz† SN74AUP1G74 LOW-POWER SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES644A – MARCH 2006 – REVISED SEPTEMBER 2006 Figure 1. AUP – The Lowest-Power Family Figure 2. Excellent Signal Integrity This single positive-edge-triggered D-type flip-flop is designed for 0.8-V to 3.6-V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L X L X X L H H H ↑ H H L H H ↑ L L H H H L X Q0 Q 0 2 Submit Documentation Feedback |
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