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AD7785 데이터시트(HTML) 4 Page - Analog Devices

부품명 AD7785
상세내용  3-Channel, Low Noise, Low Power, 20-Bit ∑-Δ ADC with On-Chip In-Amp and Reference
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제조사  AD [Analog Devices]
홈페이지  http://www.analog.com
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AD7785 데이터시트(HTML) 4 Page - Analog Devices

 
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AD7785
Rev. 0 | Page 4 of 32
Parameter
AD7785B1
Unit
Test Conditions/Comments
REFERENCE
Internal Reference
Internal Reference Initial Accuracy
1.17 ± 0.01%
V min/max
AVDD = 4 V, TA = 25°C
Internal Reference Drift2
4
ppm/°C typ
15
ppm/°C max
Power Supply Rejection
85
dB typ
External Reference
External REFIN Voltage
2.5
V nom
REFIN = REFIN(+)
− REFIN(−)
Reference Voltage Range2
0.1
V min
AVDD
V max
When VREF = AVDD, the differential input must be
limited to 0.9 × VREF /gain if the in-amp is active
Absolute REFIN Voltage Limits2
GND
− 30 mV
V min
AVDD + 30 mV
V max
Average Reference Input Current
400
nA/V typ
Average Reference Input Current
Drift
±0.03
nA/V/°C typ
Normal Mode Rejection
Same as for analog inputs
Common-Mode Rejection
100
dB typ
EXCITATION CURRENT SOURCES
(IEXC1 and IEXC2)
Output Current
10/210/1000
μA nom
Initial Tolerance at 25°C
±5
% typ
Drift
200
ppm/°C typ
Current Matching
±0.5
% typ
Matching between IEXC1 and IEXC2; VOUT = 0 V
Drift Matching
50
ppm/°C typ
Line Regulation (VDD)
2
%/V typ
AVDD = 5 V ± 5%
Load Regulation
0.2
%/V typ
Output Compliance
AVDD
− 0.65
V max
10 μA or 210 μA currents selected
AVDD
− 1.1
V max
1 mA currents selected
GND
− 30 mV
V min
TEMPERATURE SENSOR
Accuracy
Sensitivity
±2
0.81
°C typ
mV/°C typ
Applies if user calibrates the temperature sensor
Applies if user calibrates the temperature sensor
BIAS VOLTAGE GENERATOR
VBIAS
AVDD/2
V nom
VBIAS Generator Start-Up Time
See Figure 10
ms/nF typ
Dependent on the capacitance on the AIN pin
INTERNAL/EXTERNAL CLOCK
Internal Clock
Frequency2
64 ± 3%
kHz min/max
Duty Cycle
50:50
% typ
External Clock
Frequency
64
kHz nom
A 128 kHz external clock can be used if the
divide-by-2 function is used
(Bit CLK1 = CLK0 = 1)
Duty Cycle
45:55 to 55:45
% typ
Applies for external 64 kHz clock; a 128 kHz
clock can have a less stringent duty cycle
LOGIC INPUTS
CS2
VINL, Input Low Voltage
0.8
V max
DVDD = 5 V
VINH, Input High Voltage
0.4
2.0
V max
V min
DVDD = 3 V
DVDD = 3 V or 5 V


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