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MC34920EI 데이터시트(PDF) 11 Page - Freescale Semiconductor, Inc |
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MC34920EI 데이터시트(HTML) 11 Page - Freescale Semiconductor, Inc |
11 / 29 page Analog Integrated Circuit Device Data Freescale Semiconductor 11 34920 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS Figure 4. Serial Connectivity Diagram Figure 5. RESET Generation Timing Diagram (Assumes VVB+ > VVB+T+ During Entire Period) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Time SDI SDI Stays at Last Value MSB LSB SCLK Tdsu Tend Data Latched on the rising edge of SCLK nCS Tcs + SCLK Tcs - SCLK Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Time SDI SDI Stays at Last Value MSB LSB SCLK Tdsu Tend Data Latched on the rising edge of SCLK nCS Tcs + SCLK Tcs - SCLK Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Time SDI SDI Stays at Last Value MSB LSB SCLK SCLK SCLK SCLK Tdsu Tend Data Latched on the rising edge of SCLK nCS Tcs + SCLK Tcs - SCLK CS SDI SCLK Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 13* MSB LSB *SDI stays at last value tDSU tDHD Data latched on rising edge of SCLK tCS-SCLK tSCLK-CS Time Tpersist delay n RESET undefined undefined Tdelay 15-50 mS (plus Tpersist delay_ Tpersist delay VCC Short glitch below VtVCC for less than Tpersist Trip level VtVCC Trip level VtVCC 1 V Tdelay 15-50mS (plus Tpersist delay) Assumes VB+ > VtVB+ during the entire period Power On “Glitch” Response Power Off Tpersist delay n RESET undefined undefined undefined Tdelay 15-50 mS (plus Tpersist delay_ Tpersist delay VCC Short glitch below VtVCC for less than Tpersist Trip level VtVCC Trip level VtVCC 1 V Tdelay 15-50mS (plus Tpersist delay) Tdelay 15-50mS (plus Tpersist delay) Assumes VB+ > VtVB+ during the entire period Power On “Glitch” Response Power Off Power On “Glitch” Response Power Off Power On “Glitch” Response Power Off VCC RESET 1.0 V Short glitch below VV1T for less than tPERSIST Trip Level VV1T Trip Level VV1T Undefined Undefined tDELAY 15–50 ms (plus tPERSIST) tPERSIST tDELAY 15–50 ms (plus tPERSIST) tPERSIST |
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