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KMPC860DTZQ50D4 데이터시트(Datasheet) 4 Page - Freescale Semiconductor, Inc

부품명 KMPC860DTZQ50D4
상세내용  Hardware Specifications
PDF  80 Pages
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제조사  FREESCALE [Freescale Semiconductor, Inc]
홈페이지  http://www.freescale.com
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 4 page
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MPC860 Family Hardware Specifications, Rev. 7
4
Freescale Semiconductor
Features
— UTOPIA-mode ATM supports level-1 master with cell-level handshake, multi-PHY (up to four physical
layer devices), connection to 25-, 51-, or 155-Mbps framers, and UTOPIA/system clock ratios of 1/2 or
1/3.
— Serial-mode ATM connection supports transmission convergence (TC) function for T1/E1/ADSL lines,
cell delineation, cell payload scrambling/descrambling, automatic idle/unassigned cell
insertion/stripping, header error control (HEC) generation, checking, and statistics.
Communications processor module (CPM)
— RISC communications processor (CP)
— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT MODE, and
RESTART TRANSMIT
)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8 Kbytes of dual-port RAM
— 16 serial DMA (SDMA) channels
— Three parallel I/O registers with open-drain capability
Four baud-rate generators (BRGs)
— Independent (can be tied to any SCC or SMC)
— Allows changes during operation
— Autobaud support option
Four serial communications controllers (SCCs)
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation (available only on
specially programmed devices)
— HDLC/SDLC (all channels supported at 2 Mbps)
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support point-to-point protocol (PPP)
—AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame-based with optional cyclic redundancy check (CRC))
Two SMCs (serial management channels)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
One SPI (serial peripheral interface)
— Supports master and slave modes
— Supports multimaster operation on the same bus
•One I2C (inter-integrated circuit) port
— Supports master and slave modes




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