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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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KMPC860TZQ50D4 데이터시트(PDF) 50 Page - Freescale Semiconductor, Inc |
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KMPC860TZQ50D4 데이터시트(HTML) 50 Page - Freescale Semiconductor, Inc |
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50 / 80 page  MPC860 Family Hardware Specifications, Rev. 7 50 Freescale Semiconductor CPM Electrical Characteristics 75 L1RSYNC, L1TSYNC rise/fall time — 15.00 ns 76 L1RXD valid to L1CLK edge (L1RXD setup time) 17.00 — ns 77 L1CLK edge to L1RXD invalid (L1RXD hold time) 13.00 — ns 78 L1CLK edge to L1ST(1–4) valid 4 10.00 45.00 ns 78A L1SYNC valid to L1ST(1–4) valid 10.00 45.00 ns 79 L1CLK edge to L1ST(1–4) invalid 10.00 45.00 ns 80 L1CLK edge to L1TXD valid 10.00 55.00 ns 80A L1TSYNC valid to L1TXD valid 4 10.00 55.00 ns 81 L1CLK edge to L1TXD high impedance 0.00 42.00 ns 82 L1RCLK, L1TCLK frequency (DSC =1) — 16.00 or SYNCCLK/2 MHz 83 L1RCLK, L1TCLK width low (DSC =1) P + 10 — ns 83a L1RCLK, L1TCLK width high (DSC = 1)3 P + 10 — ns 84 L1CLK edge to L1CLKO valid (DSC = 1) — 30.00 ns 85 L1RQ valid before falling edge of L1TSYNC4 1.00 — L1TCL K 86 L1GR setup time2 42.00 — ns 87 L1GR hold time 42.00 — ns 88 L1CLK edge to L1SYNC valid (FSD = 00) CNT = 0000, BYT = 0, DSC = 0) — 0.00 ns 1 The ratio SYNCCLK/L1RCLK must be greater than 2.5/1. 2 These specs are valid for IDL mode only. 3 Where P = 1/CLKOUT. Thus, for a 25-MHz CLKO1 rate, P = 40 ns. 4 These strobes and TxD on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever comes later. Table 19. SI Timing (continued) Num Characteristic All Frequencies Unit Min Max |
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