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ST16C550CP40 데이터시트(PDF) 5 Page - Exar Corporation |
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ST16C550CP40 데이터시트(HTML) 5 Page - Exar Corporation |
5 / 35 page ST16C550 5 Rev. 5.01 Symbol Pin Signal Pin Description 40 44 48 type SYMBOL DESCRIPTION -IOR 21 24 19 I Read data strobe (active low strobe). A logic 0 on this pin transfers the contents of the ST16C550 data bus to the CPU. Connect to logic 1 when using IOR. -IOW 18 20 16 I Write data strobe (active low strobe). A logic 0 on this pin transfers the contents of the CPU data bus to the addressed internal register. Connect to logic 1 when using IOW. INT 30 33 30 O Interrupt Request (active high). Interrupts are enabled in the interrupt enable register (IER), and when an interrupt con- dition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected. -RXRDY 29 32 29 O Receive Ready. When operating in the FIFO mode, one of two types of DMA signaling can be selected using the FIFO control register bit-3. When operating in the ST16C450 mode, only DMA mode “0” is allowed. Mode “0” supports single transfer DMA in which a transfer is made between CPU bus cycles. Mode “1” supports multi-transfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode “0” -RXRDY is low, when there is at least one character in the receiver FIFO or receive holding register. In DMA mode “1”, -RXRDY is low, when the trigger level or the time-out has been reached. -TXRDY 24 27 23 O Transmit Ready. When operating in the FIFO mode, one of two types of DMA signaling can be selected using the FIFO control register bit-3. When operating in the ST16C450 mode, only DMA mode “0” is allowed. Mode “0” supports single transfer DMA in which a transfer is made between CPU bus cycles. Mode “1” supports multi-transfer DMA in which multiple transfers are made continuously until the transmit FIFO has been filled. -BAUDOUT 15 17 12 O Baud Rate Generator Output. This pin provides the 16X clock of the selected data rate from the baud rate generator. The RCLK pin must be connected externally to -BAUDOUT when the receiver is operating at the same data rate. |
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