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TDA1301 데이터시트(Datasheet) 7 Page - NXP Semiconductors

부품명 TDA1301
상세내용  Digital servo processor DSIC2
PDF  14 Pages
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제조사  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
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 7 page
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March 1994
8
Philips Semiconductors
Product specification
Digital servo processor (DSIC2)
TDA1301T
In combination with the radial polarity flag (RP) the relative
spot-position over the tracks can be determined. These
signals are, however, affected with some uncertainties
caused by:
• Disc defects such as scratches and fingerprints.
• The HF information on the disc, which is considered as
noise by the detector signals.
In order to determine the spot position with sufficient
accuracy, extra conditions are necessary to generate a TL
signal as well as an off-track counter value. These extra
conditions influence the maximum speed and this implies
that, internally, one of the three following counting states is
selected. These states are:
1. Protected state: used in normal play situations.
A good detection caused by disc defects is important
in this state.
2. Slow counting state: used in low velocity track jump
situations.
In this state a fast response is important rather than
the protection against disc defects (if the phase
relationship between TL and RP of a 1
2
π rad is affected
too much, the direction cannot be determined
accurately any more).
3. Fast counting state: used in high velocity track jump
situations.
Highest obtainable velocity is the most important
feature in this state.
Off-track detection
During active radial tracking, off-track detection is realized
by continuously monitoring the off-track counter value. The
off-track flag (OTD) becomes valid whenever the off-track
counter value is not equal to zero. Depending on the type
of extended S-curve the off-track counter will be reset after
3
4 extend or at the original track in the 2
1
4 track extend
mode.
Output stages
The control signals for the different actuators are 1-bit
noise shaped digital outputs at 1.0584 MHz. An analog
representation of the output signals can be achieved by
connecting a first-order low-pass filter to the outputs.
When the RST pin is held LOW, the focus, radial and
sledge output stages are 3-state.
Serial interface
To control the DSIC2 operation, a serial interface is
implemented which allows communication with a
microcontroller via a 3-line serial bus consisting of:
• Serial clock line (SICL
• Serial data line (SIDA)
• Serial control line (SILD).
The SICL line is controlled by a microcontroller and can be
completely asynchronous from the oscillator frequency of
the DSIC2. The SILD line is used for read/write control and
end-of-byte signalling.
The communication is bi-directional and processes 8-bit
words (1 byte, MSB first). The data present on the SIDA
line is clocked on the positive edge of SICL. One
information exchange consists of one command byte and
up to 7 data bytes.
The first byte defines the command, and is always input to
the DSIC2. This byte defines if data has to be written to or
read from the DSIC2. If data has to be written to the DSIC2
this byte also specifies the number of data bytes. The
number of bytes read from the DSIC2 can vary from 0 up
to 5 and only depends on how many the microprocessor
requires to read. Further information concerning the serial
protocol is available upon request.
Clock generation
The DSIC2 operates with an internal clock frequency of
approximately 4 MHz. The circuit that generates the clock
has three modes: the oscillator frequency divided by 2, 3
or 4 (software controlled). It is therefore possible to
connect a crystal or a resonator with a frequency of
8.4672, 11.2896 or 16.9344 MHz. These frequencies are
derived from today’s frequently used decoder IC
frequencies. It is also possible to drive the clock circuit with
an external clock signal. The clock buffer output (CLKO)
can supply the system clock or twice the system clock
(also switchable under software control via the serial bus)
to be used as a clock generator for other ICs. The oscillator
circuit is optimized for low power dissipation. To guarantee
optimum performance with a quartz crystal or a resonator
the gain of the oscillator can be adjusted by an external
resistor connected to the XTALref input.
Reset
The reset is controlled by means of the RST pin (active
LOW). This circuit ensures proper initialization of the
digital circuit and the output stages.
Laser drive on
The LDON pin is used to switch the laser drive OFF and
ON. It is an open-drain output. When the laser is ON, the
output has a high impedance.




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