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TDA1307 데이터시트(Datasheet) 10 Page - NXP Semiconductors

부품명 TDA1307
상세내용  High-performance bitstream digital filter
PDF  36 Pages
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제조사  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
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 10 page
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1996 Jan 08
10
Philips Semiconductors
Preliminary specification
High-performance bitstream digital filter
TDA1307
INITIALIZATION OF THE BUS RECEIVER
The microprocessor interface section is initialized
automatically by the power-on reset function, POR
(pin 20). A LOW input on POR will initiate the reset
procedure, which encompasses a functional reset plus
setting of the initial states of the control words in the
command register file. A wait time of at least one audio
sample time after a LOW-to-HIGH transition of POR must
be observed before communication can successfully be
established between the TDA1307 and the
microprocessor. In addition to the POR function, a
software reset function issued from the microprocessor is
provided (see section “Organization and programming of
the internal register file”), which has the sole function of
reinstating the initial values of the microprocessor control
register. More information on initializing the TDA1307 can
be found under “Application Information”.
COMMAND PROTOCOL
The protocol for writing data to the TDA1307 is illustrated
in Fig.7. The command mode is invoked by forcing RAB
LOW. A unit command is given in the form of an 8-bit burst
on the DA line, clocked on the rising edge of CL.
The command consists of 4 address bits followed by
4 control data bits (both MSB first). A next command may
be immediately issued while keeping RAB forced LOW.
Only commands for which the MSB of the address bits is
LOW are accepted; of the remaining set of addresses, only
four have meaning (see section “Organization and
programming of the internal register file”). The command
input receiver is provided with a built-in protection against
erroneous command transfer due to spikes, by a 2-bit
debounce mechanism on lines DA and CL. The
waveforms on these lines are sampled by the receiver at
the internal system clock rate 256fs. A state transition on
DA or CL is accepted only when the new state perseveres
for two consecutive sampled waveform instants.
ORGANIZATION AND PROGRAMMING OF THE INTERNAL
REGISTER FILE
Command data received from the microprocessor is
stored in an internal register file (see Table 2), which is
organized as a page of 10 registers, each containing a
4-bit command data word (D3 to D0). Access to the words
in the register file involves two controls: selection of the
address of a set of registers (by means of A3, A2,
A1 and A0) and setting the number of the bank in which
the desired register is located (by means of the ‘bank bits’
B0 and B1). First the desired bank is selected by
programming the command word at address 0000
(supplying the bank bits plus refreshing bits ATT and DIM).
A subsequent addressing (one of three addresses, 1H, 4H
and 6H) will yield access to the register corresponding to
the last set bank.
Fig.7 Microprocessor command protocol.
handbook, full pagewidth
MGB995
tDRW
tCKL
tCKH
tDSM
tDHM
t
8
1
A3
A2
A1
A0
D3
D2
D1
D0
A3
A2
A1
A0
D3
D2
D1
D0
RAB
CL
DA (
µP)
DA
DA (TDA1307)




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