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TDA1311A 데이터시트(Datasheet) 10 Page - NXP Semiconductors

부품명 TDA1311A
상세내용  Stereo Continuous Calibration DAC CC-DAC
PDF  20 Pages
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제조사  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
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 10 page
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1995 Dec 18
10
Philips Semiconductors
Preliminary specification
Stereo Continuous Calibration DAC
(CC-DAC)
TDA1311A
APPLICATION INFORMATION
Basic application example
A typical example of a CD-application with the TDA1311A; AT is shown in Fig.6. It features typical decoupling
components and a third-order analog post-filter stage providing a line output.
Fig.6 Example of a 3rd order filter application.
handbook, full pagewidth
100 pF
22 k
420 pF
22 k
2.2 nF
TDA1311A
TDA1311AT
5
8
7
6
4
1
2
3
BCK
WS
DATA
100 pF
22 k
420 pF
22 k
2.2 nF
100
nF
47
µF
VDD
10
MBG863
Attention to printed circuit board layout
The TDA1311A and even more so the TDA1311AT offers
great ease in designing-in to printed-circuit boards due to
its small size and low pin count. The TDA1311A; AT being
a mixed-signal IC in CMOS, some attention needs to be
paid to layout and topology of the application PCB.
Following some basic rules will yield the desired
performance. The most important considerations are:
1. Supply: care should be taken to supply the
TDA1311A; AT with a clean, noiseless VDD, for a good
noise performance of the analog parts of the DAC.
Supply purity can easily be achieved by using an
RC-filtered supply.
2. Grounding: preferably a ground plane should be used,
in order to have a low-impedance return available at
any point in the layout. It is advantageous to make a
partitioning of the ground plane according to the nature
of the expected return currents (digital input returns
separate from supply returns and separate from the
analog section).
3. Topology: the capacitor decoupling high-frequency
supply interference from VDD to GND should be placed
as close as is physically possible to the IC body,
ensuring a low-inductance path to ground. The digital
input conductors may be shielded by ground leads
running alongside. The placement of a passive ground
plane underside the entire IC surface gives `free`
additional decoupling from the IC body to ground as
well as providing a shield between the digital input pins
and the analog output pins.
Figure 7 shows recommended layouts for printed-circuit
boards for the SO8 and DIL8 versions respectively. Both
layouts use a single-interconnect layer.




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