August 1994

13

Philips Semiconductors

Product specification

Quadruple filter DAC

TDA1314T

APPLICATION INFORMATION

The application diagram is illustrated in Fig.6.

All pins used for testing (pins 1, 2, 23, 27 and 28 need not

to be connected due to internal resistors being connected

to ground or being used as test outputs. In the normal

free-running mode it is also not required to connect pin 3.

Jitter on the clock edges of MCLK must be as low as

possible so as not to deteriorate the DAC THD

performance. The jitter time must not be greater than

30 ns.

divider. A capacitor of 22

µF is used to get the specified

power ripple rejection ratio.

The output operational amplifiers are current-to-voltage

converters by means of the 3 kW resistors connected

between the DAC current outputs (pins 10, 12, 17 and 19)

and the voltage outputs (pins 11, 13, 18 and 20)

respectively. The voltage on the DAC current outputs is

the event that the operational amplifier is used according

to the application diagram of Fig.6.

Care should be taken, in order to reduce the

electromagnetic compatibility (EMC) that the bandwidth of

the digital signals being applied to pins MCLK, WS, SCK,

SDF and SDR is not larger than necessary. This can be

achieved by controlling the slew rate of the digital source

outputs or connecting a series resistor close to the digital

source output of the driving circuits.

substrate and has the most negative voltage of the IC, a

large as possible ground plane is therefore recommended.

resistor (25

Ω). This resistor must be connected as close

as possible to pin 8.

The POWER-UP (pin 22) is connected via an electrolytic

capacitor to ground. This results in a smooth rising of the

DAC output currents at power-on. If this is not required

then this capacitor can be omitted.

Suppression of the higher harmonics by the up-sample

filter should be sufficient to protect the amplifiers and the

tweeter loudspeakers from excessive HF noise. The band

only attenuated by the sample-and-hold effect of the DAC.

At frequencies above 100 kHz, additional attenuation

achieved by the 1st order post filter, which is built around

the buffer operational amplifiers. In total a 2nd order level

of filtering can be found above 100 kHz. In terms of power

the audio out-of-band power is approximately 15

the audio in-band power.