전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

SN74VMEH22501AZQLR 데이터시트(PDF) 6 Page - Texas Instruments

부품명 SN74VMEH22501AZQLR
상세설명  8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
Download  30 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

SN74VMEH22501AZQLR 데이터시트(HTML) 6 Page - Texas Instruments

Back Button SN74VMEH22501AZQLR Datasheet HTML 2Page - Texas Instruments SN74VMEH22501AZQLR Datasheet HTML 3Page - Texas Instruments SN74VMEH22501AZQLR Datasheet HTML 4Page - Texas Instruments SN74VMEH22501AZQLR Datasheet HTML 5Page - Texas Instruments SN74VMEH22501AZQLR Datasheet HTML 6Page - Texas Instruments SN74VMEH22501AZQLR Datasheet HTML 7Page - Texas Instruments SN74VMEH22501AZQLR Datasheet HTML 8Page - Texas Instruments SN74VMEH22501AZQLR Datasheet HTML 9Page - Texas Instruments SN74VMEH22501AZQLR Datasheet HTML 10Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 30 page
background image
SN74VMEH22501A
8BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1BIT BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3STATE OUTPUTS
SCES620 – DECEMBER 2004
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC and BIAS VCC
−0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1)
−0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1)
−0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, VO
(see Note 1): 3A port or Y output
−0.5 V to VCC + 0.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port
−0.5 V to 4.6 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current in the low state, IO: 3A port or Y output
50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port
100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current in the high state, IO: 3A port or Y output
−50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B port
−100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0)
−50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC): B port
−50 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance,
θJA (see Note 2): DGG package
70
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package
58
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GQL package
42
°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg
−65
°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES:
1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Notes 3 and 4)
MIN
TYP
MAX
UNIT
VCC,
BIAS VCC
Supply voltage
3.15
3.3
3.45
V
VI
Input voltage
Control inputs or A port
VCC
5.5
V
VI
Input voltage
B port
VCC
5.5
V
VIH
High-level input voltage
Control inputs or A port
2
V
VIH
High-level input voltage
B port
0.5 VCC + 50 mV
V
VIL
Low-level input voltage
Control inputs or A port
0.8
V
VIL
Low-level input voltage
B port
0.5 VCC − 50 mV
V
IIK
Input clamp current
−18
mA
IOH
High-level output current
3A port and Y output
−12
mA
IOH
High-level output current
B port
−48
mA
IOL
Low-level output current
3A port and Y output
12
mA
IOL
Low-level output current
B port
64
mA
∆t/∆v
Input transition rise or fall rate
Outputs enabled
10
ns/V
∆t/∆VCC
Power-up ramp rate
20
µs/V
TA
Operating free-air temperature
−40
85
°C
NOTES:
3. All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4. Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and
VCC = 3.3 V last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence
is acceptable, but generally, GND is connected first.


유사한 부품 번호 - SN74VMEH22501AZQLR

제조업체부품명데이터시트상세설명
logo
Texas Instruments
SN74VMEH22501A-EP TI1-SN74VMEH22501A-EP Datasheet
545Kb / 27P
[Old version datasheet]   8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SN74VMEH22501A-EP TI-SN74VMEH22501A-EP Datasheet
545Kb / 27P
[Old version datasheet]   Enhanced Diminishing Manufacturing Sources (DMS) Support, Enhanced Product-Change Notification
SN74VMEH22501A-EP TI1-SN74VMEH22501A-EP Datasheet
929Kb / 38P
[Old version datasheet]   8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers
SN74VMEH22501A-EP TI1-SN74VMEH22501A-EP_15 Datasheet
929Kb / 38P
[Old version datasheet]   8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers
More results

유사한 설명 - SN74VMEH22501AZQLR

제조업체부품명데이터시트상세설명
logo
Texas Instruments
SN74VMEH22501A-EP TI1-SN74VMEH22501A-EP Datasheet
545Kb / 27P
[Old version datasheet]   8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SN74VMEH22501 TI-SN74VMEH22501_10 Datasheet
569Kb / 31P
[Old version datasheet]   8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS
SN74VMEH22501 TI-SN74VMEH22501 Datasheet
442Kb / 25P
[Old version datasheet]   8 BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1 BIT BUS TRANSCEIVERS WITH SPLIT LVTTL PORT FEEDBACK PATH AND 3 STATE OUTPUTS
SN74VMEH22501A-EP TI1-SN74VMEH22501A-EP_15 Datasheet
929Kb / 38P
[Old version datasheet]   8-Bit Universal Bus Transceiver and Two 1-Bit Bus Transceivers
SN74GTLP1395 TI-SN74GTLP1395 Datasheet
443Kb / 21P
[Old version datasheet]   TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP21395 TI-SN74GTLP21395 Datasheet
438Kb / 21P
[Old version datasheet]   TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
logo
Fairchild Semiconductor
GTLP10B320 FAIRCHILD-GTLP10B320 Datasheet
261Kb / 12P
   10-Bit LVTTL/GTLP Transceiver with Split LVTTL Port and Feedback Path
GTLP1B151 FAIRCHILD-GTLP1B151 Datasheet
112Kb / 7P
   1-Bit LVTTL/GTLP Transceiver with Separate LVTTL Port and Feedback Path
logo
Texas Instruments
SN74GTLP1394 TI-SN74GTLP1394_07 Datasheet
741Kb / 25P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SN74GTLP1394 TI1-SN74GTLP1394_15 Datasheet
890Kb / 23P
[Old version datasheet]   2-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVER WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30


데이터시트 다운로드

Go To PDF Page


링크 URL




개인정보취급방침
ALLDATASHEET.CO.KR
ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com