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TDA6502A 데이터시트(PDF) 11 Page - NXP Semiconductors |
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11 / 44 page 2000 Mar 16 11 Philips Semiconductors Preliminary specification 5 V mixers/oscillators and synthesizers for cable TV and VCR 2-band tuners TDA6502; TDA6502A; TDA6503; TDA6503A Table 8 Reference divider ratio select bits 8.2.3 READ MODE The read mode is defined by the address byte ADB with bit R/W = 1 (see Table 9). After the slave address has been recognized, the device generates an acknowledge pulse and status byte SB is transferred on the SDA line (MSB first). Data is valid on the SDA line during a HIGH level of the SCL line. A second data byte can be read from the device if the microcontroller generates an acknowledge on the SDA line (master acknowledge). End of transmission will occur if no master acknowledge occurs. The device will then release the data line to allow the microcontroller to generate a STOP condition. Bit POR is set to logic 1 at power-on. The bit is reset when an end-of-data is detected by the device (end of a read sequence). Control of the loop is made possible with bit FL which indicates when the loop is locked (bit FL = 1) A built-in ADC input is available on pin LOCK/ADC (I2C-bus mode only). This converter can be used to apply AFC information to the microcontroller of the IF section of the television. Table 9 Read data format Note 1. MSB is transmitted first. Table 10 Description of the bits used in Table 9 RSA RSB REFERENCE DIVIDER RATIO FREQUENCY STEP (kHz) X 0 80 50 0 1 128 31.25 1 1 64 62.5 NAME BYTE BIT MSB(1) LSB Address byte ADB 1 1 0 0 0 MA1 MA0 R/W=1 Status byte SB POR FL R 1 1 A2 A1 A0 BIT DESCRIPTION MA1 and MA0 programmable address bits (see Table 6) R/W logic 1 for read mode POR Power-on reset flag: logic 0: at power-off logic 1: at power-on FL in-lock flag: logic 0: loop is not locked logic 1: loop is locked R ready flag: logic 0: mode after Power-on reset (bit T2 = 0, bit T1 = 0 and bit T0 = 1) and the PLL is locked logic 1: in other conditions A2, A1 and A0 digital outputs of the 5-level ADC (see Table 11) |
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