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SN74LV594ADG4 데이터시트(PDF) 2 Page - Texas Instruments |
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SN74LV594ADG4 데이터시트(HTML) 2 Page - Texas Instruments |
2 / 20 page SN54LV594A, SN74LV594A 8BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) The shift-register (SRCLK) and storage-register (RCLK) clocks are positive-edge triggered. If the clocks are tied together, the shift register always is one clock pulse ahead of the storage register. FUNCTION TABLE INPUTS FUNCTION SER SRCLK SRCLR RCLK RCLR FUNCTION X X L X X Shift register is cleared. L ↑ H X X First stage of shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of shift register goes high. Other stages store the data of previous stage, respectively. L ↓ H X X Shift register state is not changed. X X X X L Storage register is cleared. X XX ↑ H Shift register data is stored in the storage register. X X X ↓ H Storage register state is not changed. |
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