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TDA8712 데이터시트(PDF) 8 Page - NXP Semiconductors

부품명 TDA8712
상세설명  8-bit digital-to-analog converters
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제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

TDA8712 데이터시트(HTML) 8 Page - NXP Semiconductors

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June 1994
8
Philips Semiconductors
Product specification
8-bit digital-to-analog converters
TDA8712; TDF8712
Notes
1. D0 to D7 are connected to VCCD and CLK is connected to DGND.
2. The analog output voltages (VOUT and VOUT) are negative with respect to VCCA (see Table 1). The output resistance
between VCCA and each of these outputs is typically 75 Ω.
3. The
−3 dB analog output bandwidth is determined by real time analysis of the output transient at a maximum input
code transition (code 0 to 255).
4. The worst case characteristics are obtained at the transition from input code 0 to 255 and if an external load
impedance greater than 75
Ω is connected between VOUT or VOUT and VCCA. The specified values have been
measured with an active probe between VOUT and AGND. No further load impedance between VOUT and AGND has
been applied. All input data is latched at the rising edge of the clock. The output voltage remains stable (independent
of input data variations) during the HIGH level of the clock (CLK = HIGH). During a LOW-to-HIGH transition of the
clock (CLK = LOW), the DAC operates in the transparent mode (input data will be directly transferred to their
corresponding analog output voltages; see Fig.5.
5. The data set-up time (tSU;DAT) is the minimum period preceding the rising edge of the clock that the input data must
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge of the clock and still be recognized. The data hold time (tHD;DAT) is the minimum period following the rising
edge of the clock that the input data must be stable in order to be correctly registered. A negative hold time indicates
that the data may be released prior to the rising edge of the clock and still be recognized.
6. The definition of glitch energy and the measurement set-up are shown in Fig.6. The glitch energy is measured at the
input transition between code 127 and 128 and on the falling edge of the clock.
Switching characteristics (fclk = 50 MHz; notes 4 and 5; see Figs 3, 4 and 5)
tSU;DAT
data set-up time
−0.3
−−
ns
tHD;DAT
data hold time
2.0
−−
ns
tPD
propagation delay time
−−
1.0
ns
tS1
settling time 1
10% to 90% full-scale
change to
±1 LSB
1.1
1.5
ns
tS2
settling time 2
10% to 90% full-scale
change to
±1 LSB
6.5
8.0
ns
td
input to 50% output delay time
3.0
5.0
ns
Output transients (glitches; fclk = 50 MHz; note 6; see Fig.6)
Eg
glitch energy from code
transition 127 to 128
−−
30
LSB
⋅ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT


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