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STK11C68-SF25TR 데이터시트(PDF) 2 Page - Simtek Corporation |
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STK11C68-SF25TR 데이터시트(HTML) 2 Page - Simtek Corporation |
2 / 16 page 2 February, 2007 Document Control #ML0007 Rev 0.3 STK11C68 (SMD5962–92324) PIN CONFIGURATIONS NC A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VCC NC A8 A9 A11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 DQ7 DQ6 DQ5 DQ4 DQ3 A12 W G E PIN NAMES Pin Name I/O Description A12-A0 Input Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array DQ7-DQ0 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM E Input Chip Enable: The active low E input selects the device W Input Write Enable: The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E G Input Output Enable: The active low G input enables the data output buffers during read cycles. De-asserting G high caused the DQ pins to tri-state. VCC Power Supply Power: 5.0V, ±10% VSS Power Supply Ground 28-Pin DIP 28-Pin SOIC 28-Pin LCC |
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